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younggeun
Visitor
Visitor
689 Views
Registered: ‎12-21-2020

ddr4 mig problem

Hello, I am using virtex us+ 7p.

for driving ddr4, i implemented the mig.

after synthesis & implementation, i programmed the bit file and ltx file into fpga.

but this problem appears as below.

younggeun_0-1620370939809.png

[Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built.
Parameter Map Version: 0, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0

this message also appeared.

INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf ddr4_0_0/bd_0/ip/ip_0/data/mb_bootloop_le.elf 

the relevant elf files are successfully populated.

 

So, I checked the reset signal and clock.

younggeun_1-1620371128401.png

reset signal and clock status are good. but init_calb_complete signal is not asserted.

 

How can i solve this problem??

 

 

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7 Replies
kren
Moderator
Moderator
681 Views
Registered: ‎08-21-2007

Did you provide a reset pulse after the input clock become stable? 

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younggeun
Visitor
Visitor
657 Views
Registered: ‎12-21-2020

@kren

Yes I also tried to input the reset pulse(ddr4_sys_rst) externally as below.

younggeun_0-1620374613358.png

after de-asserting reset(ddr4_sys_rst), the status is same.

still init_calib_complete is not asserted.

 

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kren
Moderator
Moderator
633 Views
Registered: ‎08-21-2007

Set reset=0 before the clock lock and then give a reset pulse for minimum 5ns.

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younggeun
Visitor
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Registered: ‎12-21-2020

@kren 

according to your instruction, reset is held 0 as a default.

and after few time, i asserted the reset as high. but init_calib_complete signal is still 0.

by the way, for mig 2.2 ip, there is no lock status indicator of mig's mmcm.

how can i know whether ddr mig ip's mmcm lock status is high or not??

 

and about reset logic of mig is as below.

assign ddr4_sys_rst = (~pcie_clk_lock)|mig_ddr4_reset;

always @ (posedge ddr4_ui_clk )begin
ddr4_aresetn <= ~ddr4_ui_clk_sync_rst;
end

mig_ddr4_reset is low as default.

pcie_clk_lock(from other mmcm lock signal) is high status right after programming bit file.

 

 

 

Thanks

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kren
Moderator
Moderator
537 Views
Registered: ‎08-21-2007

Modify reset logic as: assign ddr4_sys_rst = pcie_clk_lock & mig_ddr4_reset; 

Some time after power on,  assert mig_ddr4_reset=1 and the then deassert it.

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younggeun
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Registered: ‎12-21-2020

@kren 

thank you for the instruction.

i modified the reset logic as you mentioned.(mig_ddr4_reset's default value is low)

after programming ltx and bit file in open hw of vivado, i asserted mig_ddr4_reset high and de-asserted it.

But init_calib_complete is stll low.

younggeun_0-1620695380425.png

 

when i assert mig_ddr4_reset,

younggeun_1-1620695443784.png

when i de-assert mig_ddr4_reset again.

younggeun_2-1620695500646.png

 

thank you.

 



 

 

 

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kshimizu
Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎03-04-2018

Hello @younggeun ,

 

I think you have some modules in your design such as pcie, mig and so on.  To identify the cause, please try to conduct only one MIG IP.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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