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sraza
Explorer
Explorer
6,403 Views
Registered: ‎03-13-2012

in appropriate address width I guess

Hello all,

 

The MIG has designed while creation generated the address width to be something like this

 

constant ADDR_WIDTH : integer := 29;
-- # = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;

 

Now I dont remember where I read and also couldnot find again that since the DDR3 that I am using has only 1 rank,

hence the Rank_width should be ZERO.

Hence the default width created by MIG is 29 while in actual it should be 28.

 

What if I change the width to 28 by myself, I am not sure if it will positively affect the design as per my need (i.e. without any rank DDR3)

 

What is the proper rememdy

 

Thanks

 

waiting...!

Shan

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5 Replies
gszakacs
Instructor
Instructor
6,396 Views
Registered: ‎08-14-2007

You don't say which version of MIG, but this looks remarkable like Spartan 6, where the address

width is 29:0 (actually 30 bits) regardless of the amount of attached memory.  Normally you just figure

out which bits really control the memory and make sure the others are always zero.  If you don't

hook them up, it might work because undriven nets get grounded during synthesis.  However I would

expect problems in simulation.

-- Gabor
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sraza
Explorer
Explorer
6,393 Views
Registered: ‎03-13-2012

No this is virtex 6 and MIG 3.8

 

I have something related to addressing. If you can then I discuss my problem...

I have already discussed in this forum but no one answer till now...

 

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gszakacs
Instructor
Instructor
6,391 Views
Registered: ‎08-14-2007

O.K.  are you sure you have correctly configured the core for the device(s) you are using?  It would

seem that ADDR_WIDTH should be generated based on the configuration (device type, number of

ranks) that you gave the customizer.

 

What memory device are you using?

-- Gabor
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sraza
Explorer
Explorer
6,387 Views
Registered: ‎03-13-2012

I am using MT41J256M16EIDT from micron .

and this device I made throught he custom part option since it was not orignally present there.

 

It has 1 rank hence for one rank, 15 bit row addres, 10 bit Col address, 3 bit bank address it makes 28 bit address.

and I am pretty much sure I made the correct configuration. since I ran the example test as well with the DDR3 part as well...

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hengel
Visitor
Visitor
6,354 Views
Registered: ‎08-24-2009

Hello,

 

I also think there is some inconsistency for the generated ADDR_WITH. These are bit widths of different SO-DIMM parameters fed into MIG 3.91/ISE14.1 for Virtex-6 and the generated ADDR_WIDTH paramerter:

ModuleSizeRowColBank#RanksADDR_WIDTH
MT4JSF6464HY 512MB 13 10 3 1 27
MT4JSF12864HZ 1GB 14 10 3 1 28
M471B5673EH1 2GB 14 10 3 2 28
MT16JSF51264H2 4GB 15 10 3 2 29

MIG creates the same ADDR_WIDTH for modules of different sizes. To my feeling ADDR_WIDTH is one bit to large for single ranked devices: RANK_WIDTH is 1 regardless of module type, IMHO it should be 0 for single ranked ones. The reason why the MIG example design still works for all modules is that the END_ADDRESS value of the TrafficGenerator is by default x"00ffffff" regardless of which module is chosen (at least for the 4 modules listed above).

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