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fvnktion
Visitor
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Registered: ‎10-31-2007

lenth matching rules for 7 series DDR2

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Hi There,

 

I am designing an artix 7 board with DDRS which will interface to the hard memory controller.  I cannot find any series 7 DDR2 length matching specific rules for these devices, though DDR3 is mentioned in UG586 P.122  "Design Guidelines>DDR3 SDRAM>Trace Lengths":

 

Trace Lengths

* The maximum electrical delay between any DQ and its associated DQS/DQS# should
be ±5 ps.
• The maximum electrical delay between any address and control signals and the
corresponding CK/CK# should be ±25 ps.
• The maximum electrical delay of any DQS/DQS# should be less than that of
CK/CK#.
DQ to DQS matching can be relaxed by the change in clock period as the frequency is
lowered from the maximum. For example, if the maximum supported frequency for a
configuration is 533 MHz, then the bit time at this frequency is 937.5 ps. The DQ to DQS
PCB skew is allowed to be +/- 5ps. If this design is operated at 400 MHz, the bit time is
1250 ps. The change in period is 1250 minus 937.5 or 312.5 ps. Half of this is 156 ps. Thus
the new skew allowed is +/- (156+5) or +/- 161 ps.

 

This data is for running DDR3.  Does this apply to DDR2.  Why is DDR2 not mentioned?

 

Thanks.

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
20,515 Views
Registered: ‎07-11-2011

HI

 

@fvnktion 

 

UG586 Chapter-1 "DDR3 and DDR2 SDRAM Memory Interface Solution" concepts mostly apply for DDR3 and DDR2 as well.

For DDR2 The maximum electrical delay between any DQS/DQS# and CK/CK# must be < ±25 ps and is for max data rates of DDR2 for that specific 7 series device which can be found in device specific datasheets.

 

But even the latest UG586-v2.3 design guidliness of DDR2 do not have derating section so the same concept as that of DDR3 applies to DDR2 as well.

 

On your second question MIG do not support DDR interface, but if in case you would like to have your own phy and controller and looking for layout guidlienss general info can be followed and I think below links can give a better information

 

http://www.google.co.in/url?url=http://www.micron.com/~/media/Documents/Products/Technical%2520Note/DRAM/tn4614.pdf&rct=j&frm=1&q=&esrc=s&sa=U&ei=VSaFVOfhF4iRuASl-oCwAg&ved=0CBoQFjAB&usg=AFQjCNGMwiTEYXTg_v2AWacCoSDVf33_6w

 

http://www.icd.com.au/articles/DDR_Design_Part_1_PCB-May2011.pdf

http://www.icd.com.au/articles/DDR_Design_Part_2_PCB-June2011.pdf

 

Specific to 7 series you can run IBIS simulations and verify the SI of your board, please go through below link and its sublinks for detailed information

http://www.xilinx.com/products/design_resources/signal_integrity/si_whyibis.htm

 

Hope this helps

 

-Vanitha

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fvnktion
Visitor
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Registered: ‎10-31-2007

Also, are there any other suggested PCB guides or documentation relative to teh DDR layout?  The UG483 "7 Series FPGAs
PCB Design Guide" has no guidance relative to DDR.  

 

Thanks.

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yenigal
Xilinx Employee
Xilinx Employee
12,445 Views
Registered: ‎02-06-2013

Hi

 

 

Looks like you are referring old User guide,the latest ug does include the design guidelines for DDR2 also.

 

Have a look at DDR2 SDRAM subsection of Design guidelines of the below doc

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf

Regards,

Satish

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vsrunga
Xilinx Employee
Xilinx Employee
20,516 Views
Registered: ‎07-11-2011

HI

 

@fvnktion 

 

UG586 Chapter-1 "DDR3 and DDR2 SDRAM Memory Interface Solution" concepts mostly apply for DDR3 and DDR2 as well.

For DDR2 The maximum electrical delay between any DQS/DQS# and CK/CK# must be < ±25 ps and is for max data rates of DDR2 for that specific 7 series device which can be found in device specific datasheets.

 

But even the latest UG586-v2.3 design guidliness of DDR2 do not have derating section so the same concept as that of DDR3 applies to DDR2 as well.

 

On your second question MIG do not support DDR interface, but if in case you would like to have your own phy and controller and looking for layout guidlienss general info can be followed and I think below links can give a better information

 

http://www.google.co.in/url?url=http://www.micron.com/~/media/Documents/Products/Technical%2520Note/DRAM/tn4614.pdf&rct=j&frm=1&q=&esrc=s&sa=U&ei=VSaFVOfhF4iRuASl-oCwAg&ved=0CBoQFjAB&usg=AFQjCNGMwiTEYXTg_v2AWacCoSDVf33_6w

 

http://www.icd.com.au/articles/DDR_Design_Part_1_PCB-May2011.pdf

http://www.icd.com.au/articles/DDR_Design_Part_2_PCB-June2011.pdf

 

Specific to 7 series you can run IBIS simulations and verify the SI of your board, please go through below link and its sublinks for detailed information

http://www.xilinx.com/products/design_resources/signal_integrity/si_whyibis.htm

 

Hope this helps

 

-Vanitha

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fvnktion
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Registered: ‎10-31-2007

Thank you!  Indeed I missed the latest version of the UG586.  

 

Thank you for the great links as well!  Such a daunting task for the first time.  Very thankful for xilnix and others' great app notes.

 

I did find what seems to be a contradiction from the following rule found in UG586 V2.3 P. 195:

"CK must be connected to a p-n pair in one of the control byte groups. Any p-n pair in the group is acceptable, including SRCC, MRCC, and DQS pins."

 

The UCF file generated from MIS assigned the CKp/n pin on a byte group outside of the "control byte groups" as specified by this rule.  The ADDR/CTL groups are Bank15 T1/T2 and MIS placed the CK pin in T3.  Do you see this as a problem where it it is an adjacent byte group?

 

Thanks.

 

 

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yenigal
Xilinx Employee
Xilinx Employee
12,387 Views
Registered: ‎02-06-2013

Hi

 

 

This rule should be followed.

 

Are you seeing this with latest version of MIG.

 

There is a known issue is old versions of MIG http://www.xilinx.com/support/answers/45633.html

 

Can you upload the Mig.prj and XDC files.

Regards,

Satish

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fvnktion
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Registered: ‎10-31-2007

Hi Satish,

 

I am using MIG 1.9 integrated in ISE 14.7.

 

Attached are the requested files.

 

The linked issue only refers to CKE and ODT not ck_p/n pins.  I suppose ck signals should be added to the known issue?

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fvnktion
Visitor
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Registered: ‎10-31-2007
This appears to be the latest MIG? If not I do not see any updates avaiable?

http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

Is there somewhere else I should be looking?
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vsrunga
Xilinx Employee
Xilinx Employee
12,372 Views
Registered: ‎07-11-2011

Hi,

 

>>CK must be connected to a p-n pair in one of the control byte groups. Any p-n pair in the group is acceptable, including SRCC, MRCC, and DQS pins

 

 

and actually in control byte group consists of  RAS_N, CAS_N, WE_N, CS_N, CKE, ODT and address lines

  

 

In your pinout CKE and ODT are placed in T3 -Bank 15 which also falls under address and control byte group so CKp/n  placement is correct and you can safely go ahead.

 

AR need not be updated.

 

Hope this helps

 

-Vanitha

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yenigal
Xilinx Employee
Xilinx Employee
12,364 Views
Registered: ‎02-06-2013

Hi

 

In the uploaded Mig.prj you can clearly see that bank T3="Address/Ctrl-2 and the generated pin out is correct.

Regards,

Satish

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vsrunga
Xilinx Employee
Xilinx Employee
9,830 Views
Registered: ‎07-11-2011

Hi,

 

>>This appears to be the latest MIG? If not I do not see any updates avaiable?  Is there somewhere else I should be looking?

 

Assuming you are using Vivado  MIG 1.9 is a bit old,   latest MIG comes with Vivado 2014.4 and has many more updates and bug fixes, so I woulld suggest you to upgrade your tools and use MIG v 2.3.

 

http://www.xilinx.com/support/answers/54025.html

 

Also I have verified your XDC and prj with MIG 2.3 and it is valid

 

 

Regards,

Vanitha

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fvnktion
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Registered: ‎10-31-2007

Indeed my ovesight.  Thanks for the help.

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