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jackdo20
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Registered: ‎07-09-2014

mig ddr3 simulation questions

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Hello everyone

 Nowadays,I am studying the DDR3 memory controller. I used the MIG to generate a DDR3 memory controller which based on zc706 board and I chose a 8GB RAM module(MT18KSF1G72PDZ) because I only want to do the simulation.

 

When I do the simulation with example design, everything was ok and modelsim showed "TEST PASSED".

 

My question is how can I do the simulation without the traffic generator?(I just want to write a simple testbench to check the memory controller)

 

Watiting for reply

Thank you

jack

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vsrunga
Xilinx Employee
Xilinx Employee
14,709 Views
Registered: ‎07-11-2011

Hi,

 

This question is something design related.

As DDR2/DDR3 is not like SRAM, access can't be done continuously.

Apart fom Write and Read, non data commands like Active, Precharge, Refresh and Zq Calibration will consume clocks at random /periodic intervals, those clocks will add up intermediate delays and user has to wait for the controller to be ready to write/read data.

 

If you have a data source that continously sends data and you have to store it in DDR3 using MIG you may use FIFO which reduces the effect of delays to some extent.

 

Hope this helps

 

Regards,

Vanitha

 

P.S:- For questions other than the current Subject please start new threads

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
This ARs will give you all the details

http://www.xilinx.com/support/answers/34243.html
Thanks and Regards
Balkrishan
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jackdo20
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Registered: ‎07-09-2014

thank you very much Balkrishan

I also searched the internet about how to do the simulation.

And I did the A type that I made a testbench by myself but "ini_calib_complete" never went high.

Also some people said they did the simulation in B type. Just removed the traffic generator and made their own traffic.

I am wondering which simulation type I should use ?

 

Thanks and Regards
Jack

simulation.jpg

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vsrunga
Xilinx Employee
Xilinx Employee
8,917 Views
Registered: ‎07-11-2011

Hi,

 

To evaluate your board we woruld recommend to use Xilinx Test Bench as it has many configurable features like command, address and data patterns

 

Once you evaluate the board, you can switch to your traffic, as this is idellay that you want.

To do that genrate example design and comment out traffic gen module and write your own FSM in place of that taking care of commands, write and read timing daigrams given in UG586

No need to modify the test bench, sim_tb_top at all

 

 

Let me know if you face any issues

 

 

Regards,

Vanitha

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jackdo20
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Registered: ‎07-09-2014
Thank you very much Vanitha
Some people told me that they used a FIFO into their own traffic.
But why do they use FIFO to transfer the data ?
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vsrunga
Xilinx Employee
Xilinx Employee
14,710 Views
Registered: ‎07-11-2011

Hi,

 

This question is something design related.

As DDR2/DDR3 is not like SRAM, access can't be done continuously.

Apart fom Write and Read, non data commands like Active, Precharge, Refresh and Zq Calibration will consume clocks at random /periodic intervals, those clocks will add up intermediate delays and user has to wait for the controller to be ready to write/read data.

 

If you have a data source that continously sends data and you have to store it in DDR3 using MIG you may use FIFO which reduces the effect of delays to some extent.

 

Hope this helps

 

Regards,

Vanitha

 

P.S:- For questions other than the current Subject please start new threads

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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jackdo20
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Registered: ‎07-09-2014
Thank you Vanitha
That helps me a lot
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