problem parameterizing Xilinx DDR4 IP block from block design tcl

[bfung]

I created a block design (containing a Xilinx DDR4 IP block) tcl file with write_bd_tcl in vivado tcl mode,

When recreating the block design by sourcing this tcl file, I get the following errors: 

ERROR: [IP_Flow 19-3461] Value 'default_100mhz_clk' is out of the range for parameter 'C0 CLOCK BOARD INTERFACE(C0_CLOCK_BOARD_INTERFACE)' for BD Cell 'ddr4_0' . Valid values are - Custom
ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'ddr4_0' . Valid values are - Custom
ERROR: [IP_Flow 19-3461] Value 'ddr4_sdram' is out of the range for parameter 'C0 DDR4 BOARD INTERFACE(C0_DDR4_BOARD_INTERFACE)' for BD Cell 'ddr4_0' . Valid values are - Custom
INFO: [IP_Flow 19-3438] Customization errors found on 'ddr4_0'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

while executing
"rdi::add_properties -dict {CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ None CONFIG.C0.BANK_GROUP_WIDTH 1 CONFIG.C0.CS_WIDTH 2 CONFIG.C0.DDR4_AxiAddressWidth 32 CON..."
invoked from within
"set_property -dict [ list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {None} CONFIG.C0.BANK_GROUP_WIDTH {1} CONFIG.C0.CS_WIDTH {2} CONFIG.C0.DDR4_AxiAddressWid..."
(procedure "create_root_design" line 90)
invoked from within
"create_root_design """
(file "master.tcl" line 486)

while executing
"source master.tcl"
(file "./create_project.tcl" line 4)

I'm using Vivado 2019.2 on Ubuntu 16.04 LTS w/ 4.15.0-76-generic

[syedz]

@bfung 

Can you share the TCL file to reproduce the issue?  Before you used write_bd_tcl, please check the values of parameters mentioned in error message for ddr4_0 bd cell. The error is complaining about invalid values assigned to the parameter. 

--Syed

[syedz]

@bfung 

Any update on this thread?

--Syed