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554 Views
Registered: ‎08-15-2017

vivado2018.1 can not generate ddr3 example , top module is invalid ?

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6666.png

above is the GUI of vivado2018.1 ,

using vivado2018.1 ,firstly ,I build a empty project ,and only add mig_7series_0 to the project, and then left click the mig_7series_0 and select ‘ Open IP Example Design’,after trying a dozen of times ,the example design  was generated succefully just for one time ,mostly there are no the exmple files,only mig_7series_0 is shown in the Desing Source path;

Proviously I have install the vivado2017.4 which this phenomenon occasionally appears too;

and now two version vivados are installed in my computer,may this infulence to generate the ddr3  example ?

do you have solution ?

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Moderator
Moderator
485 Views
Registered: ‎11-28-2016

Hello @microchip_zhang ,

Those files are to model a wire delay for the DDR3 interface which is required for the abridged calibration sequence that runs with the MIG 7-Series example design simulation.

View solution in original post

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Moderator
Moderator
537 Views
Registered: ‎11-28-2016

Hello @microchip_zhang ,

Before right clicking on the IP instance and selecting "Open IP Example Design" the output products for the IP must be complete.  Looking at your GUI it seems like the IP was generated in Out of Context mode because there's the yellow box associated with the IP instance.  I can also see that there wasn't an OOC run associated with this IP.  Therefore if you tried to generate an IP example design in this case then it would be incomplete.  Here you'll have to right click on the IP instance and select "Generate IP Output Products".  From there you can either select "Global" which will generate just the output files for the IP, which is the fastest way, then right click on the IP and select "Open IP Example Design." Otherwise you can generate with OOC, let the run finish, then open the IP example design.

Here's what a completed OOC run looks like and is now safe to open the IP Example Design:
complete_occ_run.PNG

Here's what a completed "Global" output products build looks like and is now safe to generate the IP example design:
complete_global_output_run.PNG

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Registered: ‎08-15-2017

thanks for your help,

and I have generated the example design ,and want to generate a questasim example design,

the three step is shown below,

but sim_tb_top ,ddr3_model and severial wiredelay file  is absent in the questasim project named sim_q comparing to the vivado_simulator project name sim_1,do I make any mistake?or

if I copy the sim_tb_top ,ddr3_model and severial wiredelay file to sim_tb_top of questasim project ,can the questasim project work correctly?

and what is the function of WireDelay.v module,I have learn the file,but I am not clear yet?

611.png

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Registered: ‎08-15-2017

I add sim_tb_top ,ddr3_model and severial wiredelay file via 'add source',it seems to work,

and what is the function of WireDelay.v  ?

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Highlighted
Moderator
Moderator
486 Views
Registered: ‎11-28-2016

Hello @microchip_zhang ,

Those files are to model a wire delay for the DDR3 interface which is required for the abridged calibration sequence that runs with the MIG 7-Series example design simulation.

View solution in original post

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