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160 Views
Registered: ‎10-17-2019

xapp398

I compiled the compact flash interface from xapp398 but I get the warnings below about latches detected, that they are generated from incomplete case or if statements and they should be eliminated since they can cause timing problems.

The code below generates latch warnings for io_data_r and am_data_r but not cm_data.

I thought the others statement would prevent latches from being generated.

Any suggestions will be appreciated.

Xst:737 - Found 8-bit latch for signal <io_data_r>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Xst:737 - Found 8-bit latch for signal <am_data_r>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.

 ----------------------------------------------------------  
 -- ************************ Read *************************
 ----------------------------------------------------------  
 host_data_low <=
 
   -- Attribute Memory
   am_data_r when (am_read_n = '0' and eight_even = '1') else
 
    -- Common Memory 8/16-bit mode  (even byte)
    cm_data(7 downto 0) when (cm_read_n = '0' and eight_even = '1') else
   
   -- Common Memory 8-bit mode   (odd byte)
   cm_data(7 downto 0) when (cm_read_n = '0' and eight_odd = '1') else
  
   -- Common Memory 16-bit mode   (even (LOW) & odd (HIGH) byte)
   cm_data(7 downto 0) when (cm_read_n = '0' and sixteen_even_odd = '1') else
  
    -- I/O Interface 8-bit mode (and 16 bit when enabled)  (even byte)
    io_data_r(7 downto 0) when (io_read_valid = '1' and io_read_n = '0' and eight_even = '1' and io_enab = '1') else
   
   -- I/O Interface 8-bit mode   (odd byte)
   io_data_r(7 downto 0) when (io_read_valid = '1' and io_read_n = '0' and eight_odd = '1' and io_enab = '1') else
  
   --########################################################
   -- The below is used for a 16 bit I/O space configuration
   --   -- I/O Interface 16-bit mode   (even (LOW) & odd (HIGH) byte)
   --   io_data_r(7 downto 0) when (io_read_valid = '1' and io_read_n = '0' and sixteen_even_odd = '1' and io_enab = '1') else
   --########################################################
  
   -- Standby Mode/Invalid State
   (others => 'Z');
  

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143 Views
Registered: ‎10-17-2019

Re: xapp398

Unless the latches are intentional. There doesn't seem to be a clock involved for the parts of the design where these signals are read or written. 

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