01-29-2020 01:27 AM
The PHY bring up initialization phase in PSU-init tcl hangs after some debugging, we found that the value of PSGR0 is 0x0A instead of 0x0F which means the digital delay line calibration is failed. We also checked voltages of memory parts and all of them are good.
Can you give us any debugging recommendations?
Does digital line calibration phase need any response from memory parts? or its a zynq internal problem?
02-13-2020 09:20 AM
Can you provide your full PS DDR configuration and a picture of the component you are using on the board? This could be an issue with configuration that we would need to adjust for.
Can you also do a dump of your DDR PHY and DDR Controller registers (at 0xFD080000 and 0xFD070000 and above)? That will give more detail into where you are failing calibration.
Page 456 of UG1085 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf) talks more about the Delay Line Calibration step.
Since it looks like you have not completed initialization something is probably quite off. Can you try turning on 2T timing (the config parameter is: CONFIG.PSU__DDRC__ENABLE_2T_TIMING = 1), and seeing if the register dumps seem to change? Can you also try slowing down the interface (say to 800 MHz instead of the 1200 that part can max. out at)?
Finally we have some pretty specific guidelines for PCB routing, power, and clocking that can be found in UG583 chapter 2 and for power rails in DS925. Can you look through those and double check that every one of those requirements are met? You may need to perform power and signal measurements to verify, and use a PCB simulation software to simulate the signal integrity of your board.