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Adventurer
Adventurer
497 Views
Registered: ‎08-10-2017

7 series MIG AXI - read/write at same time

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I'm using AXI interface for 7 series MIG IP for on-board 1 GB DDR3 memory in VC707 board (containing Virtex7 485T FPGA).
If the MIG gets both read request for <address1> and write request for <address2> at the same time (assuming both addresses are always different and there is no overlap in data read/written), will there be additional delay in handling those requests ?

What does this delay depend on ?

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Moderator
Moderator
620 Views
Registered: ‎11-28-2016

Re: 7 series MIG AXI - read/write at same time

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Hello @jagannath,

 

The AXI arbitration setting you selected when configuring the IP as well as the current state of the arbiter will determine what happens.  Depending on your setting and the previous traffic patterns one or the other could be selected first.  Next, once the command is translated from AXI and presented on the internal app_interface it depends on which Ordering mode you selected for the IP.  If you chose Strict ordering then whichever command was presented first will be executed first.  If you selected Normal mode then the Read command may be re-ordered before the write command.  This also depends on the bank machine availability and how address1 and address2 map to the bank machines.  This also depends on the previous access patterns, the current state of the DRAM interface as it relates to protocol, and how the Read/Write command can be scheduled depending on their target address and current state of the DRAM.

 

The AXI arbitration behavior is described on page 100 of UG586.

The Ordering modes are described on page 125 of UG586.

The Bank Machines are described on page 123 of UG586.

There's a link to UG586 is my signature.

 

 

Overall the answer to your question is very complex and requires a lot of understanding how the MIG operates and DDR3 protocol.

 

Since you're using an AXI interface then my recommendation is to not assert both Read and Write requests at the same time if you're expecting a deterministic behavior because there are many, many variables at play.

1 Reply
Moderator
Moderator
621 Views
Registered: ‎11-28-2016

Re: 7 series MIG AXI - read/write at same time

Jump to solution

Hello @jagannath,

 

The AXI arbitration setting you selected when configuring the IP as well as the current state of the arbiter will determine what happens.  Depending on your setting and the previous traffic patterns one or the other could be selected first.  Next, once the command is translated from AXI and presented on the internal app_interface it depends on which Ordering mode you selected for the IP.  If you chose Strict ordering then whichever command was presented first will be executed first.  If you selected Normal mode then the Read command may be re-ordered before the write command.  This also depends on the bank machine availability and how address1 and address2 map to the bank machines.  This also depends on the previous access patterns, the current state of the DRAM interface as it relates to protocol, and how the Read/Write command can be scheduled depending on their target address and current state of the DRAM.

 

The AXI arbitration behavior is described on page 100 of UG586.

The Ordering modes are described on page 125 of UG586.

The Bank Machines are described on page 123 of UG586.

There's a link to UG586 is my signature.

 

 

Overall the answer to your question is very complex and requires a lot of understanding how the MIG operates and DDR3 protocol.

 

Since you're using an AXI interface then my recommendation is to not assert both Read and Write requests at the same time if you're expecting a deterministic behavior because there are many, many variables at play.