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Observer tungho_xilinx
Observer
489 Views
Registered: ‎04-08-2017

About ZC706 MIG Tutorial (XTP244)

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Hi community,

I have started looking at the DDR3 memory design using the ZC706 Evaluation Kit.

The link to the design files is provided below:

   https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html#documentation

The user-guide documentation is provided below: 

   Zynq-7000 AP SoC and 7 Series FPGAs MIS v2.4

   UG586 November 18, 2015

In particular, I am trying to understand how the PHASER_IN Phase Lock Calibration works.

- UG586 - Pages 141, 231, 239: describe the calibration stages in details.

- mig_7series_v2_4_ddr_phy_init.v: describes the implementation in Verilog.

The literature mentions that back-to-back reads are required for PHASER_IN Phase Lock.

However, I can NOT understand how this process is actually implemented because I could NOT see any implementation in the state machine in the 'ddr_phy_init' file (page 2250).

May be I am missing something here. Can anyone help me with this question please ?? Is this part of Xilinx design or does it have to be implemented separately by the user ?? Or at least, where should I go in order to understand this process a little better ??

Thanks,

Have a nice day,

TH

 

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1 Solution

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Moderator
Moderator
433 Views
Registered: ‎11-28-2016

Re: About ZC706 MIG Tutorial (XTP244)

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Hello @tungho_xilinx,

 

This along with the rest of the details about the memory initialization and calibration are automatically generated by the IP and don't need any user interaction. The PHASER_IN elements are specifically only used for the MIG and don't have any user documentation.

1 Reply
Moderator
Moderator
434 Views
Registered: ‎11-28-2016

Re: About ZC706 MIG Tutorial (XTP244)

Jump to solution

Hello @tungho_xilinx,

 

This along with the rest of the details about the memory initialization and calibration are automatically generated by the IP and don't need any user interaction. The PHASER_IN elements are specifically only used for the MIG and don't have any user documentation.