03-28-2018 11:04 AM
When trying to design a diagram for the Artix-7 35T, the DDR3 component throws the following error:
Does anyone have any ideas on how to fix this? I am using 2015.4, which is used in the tutorials.
Thanks for your help.
03-28-2018 11:20 AM
The first thing I noticed was the 'tmp' directory in your path.
I would go to the Project Settings then IP and change your IP Cache settings to disabled and clear the cache. After that try recustomizing the IP and generating the output products.
03-28-2018 11:41 AM
The tmp I was referring to was this one:
c:/Users/*/Test/Test.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/_tmp/design_1_mig_7series_0_0" to "c:/Users/*/Test/Test.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0": permission denied
Have you tried resetting the output products and then regenerating them?
03-28-2018 12:54 PM
delete_ip_run [get_files -of_objects [get_fileset sources_1] /path/proj/proj.srcs/sources_1/bd/proj_design/proj_design.bd]
set_property synth_checkpoint_mode None [get_files /path/proj/proj.srcs/sources_1/bd/proj_design/proj_design.bd]
generate_target all [get_files /path/proj/proj.srcs/sources_1/bd/proj_design/proj_design.bd]
Update the paths and file names to match your design.
03-28-2018 01:02 PM
Same error as before. I entered the commands after deleting the MIG component from the diagram. When I tried to put it back in, the same error was given.
03-28-2018 01:21 PM
Here is the console log for when I try to place the MIG:
apply_board_connection -board_interface "ddr3_sdram" -ip_intf "mig_7series_0/mig_ddr_interface" -diagram "test2"
INFO: [board_interface:-100] set_property CONFIG.BOARD_MIG_PARAM ddr3_sdram [get_bd_cells -quiet /mig_7series_0]
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.0 available at C:/Xilinx/Vivado/2015.4/data/boards/board_files/arty-s7-25/E.0/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.0 available at C:/Xilinx/Vivado/2015.4/data/boards/board_files/arty-s7-50/B.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
error renaming "c:/Users/*/Test2/Test2.srcs/sources_1/bd/test2/ip/test2_mig_7series_0_0/_tmp/test2_mig_7series_0_0" to "c:/Users/*/Test2/Test2.srcs/sources_1/bd/test2/ip/test2_mig_7series_0_0/test2_mig_7series_0_0": permission denied
ERROR: [IP_Flow 19-3475] Tcl error in ::ipgui_test2_mig_7series_0_0::updateAllModelParams procedure for BD Cell '/mig_7series_0'. error renaming "c:/Users/*/Test2/Test2.srcs/sources_1/bd/test2/ip/test2_mig_7series_0_0/_tmp/test2_mig_7series_0_0" to "c:/Users/*/Test2/Test2.srcs/sources_1/bd/test2/ip/test2_mig_7series_0_0/test2_mig_7series_0_0": permission denied
INFO: [IP_Flow 19-3438] Customization errors found on '/mig_7series_0'. Restoring to previous valid configuration.
ERROR: [BD 41-245] set_property error - Customization errors found on '/mig_7series_0'. Restoring to previous valid configuration.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
apply_board_connection: Time (s): cpu = 00:00:00 ; elapsed = 00:00:12 . Memory (MB): peak = 1176.277 ; gain = 0.000
INFO: [Common 17-17] undo 'apply_board_connection -board_interface "ddr3_sdram" -ip_intf "mig_7series_0/mig_ddr_interface" -diagram "test2" '
03-28-2018 02:02 PM
Same error also occured on Vivado 2017.4. Do you know if I could call customer support about this? It is becoming quite frustrating.
03-28-2018 06:27 PM
Here is the output of the 2017.4 edition when trying to fix it:
03-29-2018 10:51 PM
I gave this a try on my PC but it has Windows 7 so I'm not sure if it will behave the same on your end.
First I downloaded the Digilent board files and added them to my Vivado directory.
Next I created a new Vivado project and targeted the Arty A7-35 board.
When the GUI loaded I selected the Create Block Design tab and then went to the Board tab
Then I double clicked to add the DDR3 controller to the block design, and I got the same error you did
Next I went to Project Manager -> Settings
Went to the IP option in the Settings window and pressed the Clear Cache button
After the cache was cleared I deleted the MIG from the BD and then added it again
When I added it the second time everything worked correctly!
Can you give this flow a try and let me know if it works?
03-30-2018 07:21 AM
03-30-2018 09:22 AM
Have you verified that the board files are installed in the proper location for Vivado 2017.4?
Can you also try this flow:
You'll see an error BD 41-1273 but you can ignore that.
03-30-2018 10:09 AM
Do you have the WebPack version of Vivado installed?
Can you go to the Xilinx Add Design Tools or Devices 2017.4 app in your Windows start menu and make sure all the Artix-7 devices are added to your install?
04-03-2018 04:40 PM
Any word about trying that other flow by adding the MIG IP and then running board automation?
What about dragging and dropping the MIG IP to the BD instead of double clicking on it?
Can you create a normal Project, go to the IP sources and search for the MIG IP, click through all the MIG IP GUI pages, and then generate output products at the end?
We did some more testing with Windows 10 and didn't reproduce the error with local or remote settings for the BD, using the webpack install of Vivado, and using a normal install but without any licenses.
04-15-2018 01:05 PM
I am using the Design Suite, I tried dragging and double clicking. Should I upgrade to the 2018.1 edition? The MIG is on the board, it just never has a DDR3 pin on it.
04-16-2018 01:21 PM
Have you tried the suggestion of generating the MIG IP in a normal Project flow instead of IPI?
Did you verify that the board files are present in your design?
I don't think upgrading would help but you can try if you want.
04-23-2018 09:19 AM
I'm not sure which part you're unsure about but for checking the board files look at this post earlier in the thread:
As for generating the MIG IP this is the flow.
05-05-2018 11:16 AM
Sorry if it has been a while since I have last responded, but would you please walk me through the customization project? I am having trouble with the System Signals Selection step. It keeps asking me for clock pins, and I am not sure which one to pick.
05-07-2018 04:05 PM
All you have to do here is select pins in banks or adjacent banks to the memory interface. For example if the memory interface is in banks 15-17 then simply select a bank (15, 16, or17), and then see which pins are available. If you select a bank and there aren't any available pins or it gives you an error if you select a pin, then select another bank. This is just a quick test to see if you can get the MIG tools to generate output products on your computer so it doesn't have to be an exact configuration.