03-11-2018 08:37 PM
Suspecting write failed due to wready stays low after certain successful write cycles
I'm currently using the Artix-7 AC701 Evaluation Board to evaluate my custom IP design, my design is connected to MIG through an axi_interconnect where I discovered unsuccessful write to DDR possibly due to wready didn't assert back after writing certain cycles.
I have checked the rdata, araddr, rready, rvalid and rlast control signals, the data kind of follows the input data pattern but at some point there is a data shift.
Situation on trying out MIG example rdf0225-ac701-mig-c-2015-1
I tried to start from the MIG example project to work back from there but i find difficulty compiling the MIG example project even following the rdf0225-ac701-mig-c-2015-1 slides instructions, the compiled bit file performance didn't follow the bit file precompiled in the ready_to_download folder inside rdf0225-ac701-mig-c-2015-1
Could anyone please kindly advise on my situation ?
Thank you so much for the help !
03-14-2018 10:34 PM
If wready goes low, the values on wdata and wvalid should be retained until the wready goes high. This should be taken care in user logic.
03-18-2018 11:31 PM
Thank you for your comment.
I'm a beginner to FPGA design especially on axi_interconnect interfaced with MIG, suppose I thought the wready signal should come back from MIG (or the DDR3 ram itself) ? Therefore, I was suspecting something wrong that causes MIG isn't response back after series of write cycles with wready signal low.
Would you please explain or provide more info on those relevant control signal handshaking mechanism ?
Thank you so much on replying.
04-10-2018 02:25 PM
The ARM AMBA AXI protocol is a very common industry standard interface that's used in millions of designs.
ARM owns the protocol and you have to be register user in order to have access:
However I'm sure with a few Google searches you will be able to find some training documentation on how AXI works.