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Explorer
Explorer
6,812 Views
Registered: ‎12-05-2016

CLOCK_DEDICATED_ROUTE set to BACKBONE

HI,

i am using mig and pci controller. i set one constraint as follows to avoid one issue related to clock.

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_i]  

at the stage of bitstream generation following error appeared,

[DRC 23-20] Rule violation (RTRES-1) Backbone resources - 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are sys_clk_i.

what i can do for correcting this?

thanks in advance,

Reshma

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10 Replies
Xilinx Employee
Xilinx Employee
6,803 Views
Registered: ‎09-20-2012

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

Hi @reshmaakhil

 

Which version of vivado are you using?

 

Is clock port driving sys_clk placed in same IO column as that of memory interface?

 

Try following the steps from AR https://www.xilinx.com/support/answers/60480.html

 

If possible upload _placed.dcp located in .runs-->impl_1 location here.

 

 

Thanks,
Deepika.
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Explorer
Explorer
6,794 Views
Registered: ‎12-05-2016

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

hi, thanks for your response. i followed the same steps, but i had a confusion in the second step, is it a command to be used in tcl console? when i did it, it ended up as an invalid command. so i added it in xdc file and tried to generate bit stream. but error message came as shown below. 

[DRC 23-20] Rule violation (RTRES-1) Backbone resources - 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are sys_clk_i.
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are sys_clk_i.
[DRC 23-20] Rule violation (RTSTAT-5) Partial antenna - 1 net(s) have a partial antenna. The problem bus(es) and/or net(s) are sys_clk_i.

regards,

Reshma

error.png
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Explorer
Explorer
6,775 Views
Registered: ‎12-05-2016

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

hi,

i am using vivado 2016.2, here i am attaching the file u asked.

regards, 

Reshma

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Explorer
Explorer
6,774 Views
Registered: ‎12-05-2016

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

hi,

i was able to do it finally. but it is not cleared, now it showing the error,

 

[DRC 23-20] Rule violation (RTRES-1) Backbone resources - 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are sys_clk_i.
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are sys_clk_i.
[DRC 23-20] Rule violation (RTSTAT-5) Partial antenna - 1 net(s) have a partial antenna. The problem bus(es) and/or net(s) are sys_clk_i.

 

one more thing,

when i executed the second step i got the output as

get_property route [get_nets sys_clk_i]
{ IOB_IBUF0 RIOI_I0 RIOI_ILOGIC0_D IOI_ILOGIC0_O { RIOI_I2GCLK_TOP0 HCLK_CMT_CK_IN0 CLK_HROW_BOT_R_CK_BUFG_CASCO10 CLK_HROW_BOT_R_CK_BUFG_CASCO10 CLK_HROW_BOT_R_CK_BUFG_CASCO10 CLK_BUFG_BUFGCTRL5_I0 } IOI_LOGIC_OUTS18_1 INT_INTERFACE_LOGIC_OUTS18 NN6BEG0 NN6BEG0 NN6BEG0 NN6BEG0 NN6BEG0 NN6BEG0 NN6BEG0 NN6BEG0 NN6BEG0 WR1BEG1 NN2BEG1 NN6BEG1 { SR1BEG1 CLK_L1 CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT CMT_TOP_R_UPPER_T_PLLE2_CLKIN1 } NW6BEG1 NW6BEG1 NW6BEG1 NE6BEG1 NE6BEG1 NE6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 { NR1BEG1 NN2BEG1 SR1BEG1 CLK0 GTXE2_COMMON_GTGREFCLK } NN6BEG1 NN6BEG1 NN6BEG1 NN6BEG1 SR1BEG1 CLK1 GTXE2_CHANNEL_GTGREFCLK }  

i couldnt see "You can see the Backbone is used, and see BB referenced in names."

what may be the reason??

thanks in advance.

Regards,

Reshma

 

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Xilinx Employee
Xilinx Employee
6,762 Views
Registered: ‎08-01-2008

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

use tcl file attached in forum post

https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-RTRES-1/m-p/488764#M9778
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
6,749 Views
Registered: ‎04-16-2012

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

Hi @reshmaakhil

 

Try the steps mentioned in the following answer record: https://www.xilinx.com/support/answers/54795.html

 

Thanks,

Vinay

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Explorer
Explorer
6,696 Views
Registered: ‎12-05-2016

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

hi,

thanks for your response. 

i followed the steps shown in the link. 

but it ended up in the following error,

[Common 17-1300] A message control rule with a rule id of '1' already exists. You can see what message control rules currently exist by using the command 'get_msg_config -rules'. Please try using a different rule id.

what is the meaning of this message? where i can change id? 

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Explorer
Explorer
6,683 Views
Registered: ‎12-05-2016

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

hi all,

thanks for the support. now bit stream generation completed without any errors. but, a new problem arised. i am using a kc705 board. processor is not detecting my board as a pcie device. what may be the reason?? please help.

regards,

Reshma

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3,766 Views
Registered: ‎04-02-2018

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

Good solution! It can help me to fix the same error in mine project. Thanks a lot!

2,302 Views
Registered: ‎04-02-2018

Re: CLOCK_DEDICATED_ROUTE set to BACKBONE

Add on the topic.

First I fixed the error as described above. It's some kind of shamanic spell. Then I found the cause of the error, at the physical level of the FPGA. The reason of this error was as follows: I used the frequency, fed to the MIG input from the PAD, at another point in the project. When I gave the reference frequency from PAD only to input of MIG's PLL, this error itself disappeared.

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