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Visitor pascalg
Visitor
700 Views
Registered: ‎04-20-2018

CR#688186

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Hi,

I'm using ISE 14.3 / kintex7
FPGA Design : my code -> axi_master_burst -> axi_interconnect(v1.06a) -> MIG -> DDR3
               100MHz        100MHz                150MHz                   150MHz

my code = autotest DDR3 : a lot of write burst then read burst to verify data
axi_interconnect is configurated with all MASTER / SLAVE as asynchronous.

Sometimes on board for one bitstream, write burst to DDR3 don't respond to the 2nd burst (bus2ip_mstwr_dst_rdy_n not detected) => same behavior at each power on
Generate a new bitstream with a different MAP "Starting Placer cost Table" (-t) resolve the problem.
All timings constraints are always met.

Between ISE 14.3 and ISE 14.7 axi_master_burst library has the same version : v1_00_a
But in 14.7, axi_master_burst_rddata_cntl.vhd is different : FIX CR#688186

What is the origin of this FIX ?
Can it explain the problem (problem during write burst but FIX on rddata so problably no) ?

It seems to be an asynchronous bug (change P&R add or remove the bug).
An idea from the origin of the bug ?

We can't change ISE version.

Regards.

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1 Solution

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Moderator
Moderator
888 Views
Registered: ‎02-11-2014

Re: CR#688186

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Hello @pascalg,

 

We do encourage customers to switch to Vivado with 7-series devices. There are far less issues and new features in Vivado that ISE will never get.

 

If you can't migrate to Vivado, then ISE 14.7 should be used as it will have the least amount of issues and newest features.

 

We do not recommend starting a new design on older tools.

 

The CR fixed an issue with AXI Master Burst and RLAST which is considered by the master burst IP even if the RVALID signal is not asserted. The AXI Master Burst IP was generating eof_n signals before completing the actual transaction. It was observed that the RLAST signal was getting asserted without RVALID signal.

 

There are several bits of code updated in axi_master_burst_rddata_cntl.vhd which have CR688186 comments next to them if you specifically want to see the differences.

 

Thanks,

Cory

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3 Replies
Scholar dpaul24
Scholar
685 Views
Registered: ‎08-07-2014

Re: CR#688186

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@pascalg,

 

May not directly address your concern but I must do a "**bleep** in the bud".

 

I'm using ISE 14.3 / kintex7

For a series7 FPGA you must use Vivado, not ISE.

 

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FPGA enthusiast!
All PMs will be ignored
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Moderator
Moderator
889 Views
Registered: ‎02-11-2014

Re: CR#688186

Jump to solution

Hello @pascalg,

 

We do encourage customers to switch to Vivado with 7-series devices. There are far less issues and new features in Vivado that ISE will never get.

 

If you can't migrate to Vivado, then ISE 14.7 should be used as it will have the least amount of issues and newest features.

 

We do not recommend starting a new design on older tools.

 

The CR fixed an issue with AXI Master Burst and RLAST which is considered by the master burst IP even if the RVALID signal is not asserted. The AXI Master Burst IP was generating eof_n signals before completing the actual transaction. It was observed that the RLAST signal was getting asserted without RVALID signal.

 

There are several bits of code updated in axi_master_burst_rddata_cntl.vhd which have CR688186 comments next to them if you specifically want to see the differences.

 

Thanks,

Cory

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Visitor pascalg
Visitor
595 Views
Registered: ‎04-20-2018

Re: CR#688186

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Thanks,
Pascal
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