08-17-2010 04:30 AM
I am trying read/write DDR3 using MIG on ML605 board. Firstly, i write 32 bursts (BL8 burst mode) at continuous address locations - incressing 8, e.g 0->8->16->....(app_addr[2:0]= "000"). Tthe adjacent write commands or read commands seperate each other 1clk cycle, then i read 32 burst with same addresss order but data out not match in order with data in. If i write, read only 24 (or smaller) bursts, above situation does not hapen.
Please help me to resolve it.
I have attached timing diagram following.
09-06-2010 12:12 AM
It is probably a good idea for you to run simulation and compare what you expect to see on DRAM interface, against the read, write command that you send.
Also making sure that error condition or underflow, overflow is not happening on user interface will help.
09-07-2010 02:18 AM
The addressing increment value for the next write/read must be calculated based on burst length and user interface port size, I think that is creating problem in your case.
09-08-2010 12:29 AM
Thanks for your reply,
I use user interface (not native interface), BL8 burst mode and burst type is sequential, data port size is APP_DATA_WIDTH = PAYLOAD_WIDTH * 4 = 256. Each write/read command accesses to 8 locations in DDR3. So I think that addressing increment value by 8 for the next write/read is correct. Here I take app_addr[2:0] always = "000" and increase app_addr[26:3] by 1. I think that it is not problem.
09-08-2010 12:55 AM - edited 09-08-2010 01:07 AM
What is the data port width on the user (fabric) side?
The address for the user port is always a byte address, regardless of the data port width. A burst length of 8 spans 8 words, not 8 bytes, so the burst increment of 8 must be multiplied by the data port word width (in bytes) when applied to the address. If the data port width is 4 bytes (32 bits), and you are specifying
cmd_bl = 5'h07 (which is a burst of 8 32-bit words)
then the address should increment by 32 (8 words * 4 bytes per word) for consecutive bursts.
(e.g. address <= address + 8'h20)
Hope this helps clear things up.
Interface Details section Table 2-5 (page 26) (see pX_cmd_bl description)
Addressing section (page 51)
Byte Address to Memory Address Conversion section (page 61) includingTable 4-5
If you think UG388 should elaborate on this a bit more (perhaps with an additional paragraph in the Addressing section), satyakumar is the Xilinx UG388 guru to whom you should make this request. :smileywink:
- Bob Elkind
09-08-2010 02:35 AM - edited 09-08-2010 03:54 AM
It appears from your simulation trace, if I interpret it correctly, that you are writing 2 WR_DATA words to the port for every WRITE command issued. This would suggest a burst length of 2, not 8.
While the address to the MCB is always a BYTE address, the BURST LENGTH specifies the number of WORDS which are written (or read), not BYTES.
Did you notice WR_UNDERRUN asserted by the write data FIFO, or RD_OVERFLOW asserted for the read data FIFO?
Tying this all together....
Assuming 32-bit data port width, and writing 2 words per burst,
- set cmd_bl = 01 (burst length is 2)
- increment app_addr[26:3] by 1 for each burst
Hope this helps --
- Bob Elkind
09-19-2010 06:12 PM
I have resolved the problem, i only change parameter ORDERING to STRICT. it's ok now.
Thank you very much.