06-01-2019 10:46 AM
I am using kintex 7 FPGA , I created MIG for DDR 3 , I went for bank row column memory mapping mode ,
I am having doubt in giving the address for this
I am reading 256 bit data from fifo and writing at the address 1 (address is 29 bit through app_addr ) , I am writing the next data from address 8 and next data from previous address +8 is it the correct way that i am to generating the address.
my assumption is address 1 will have 8 column which start from 0 to 7 so first 32 bit of 256 bit data will be written in column 0 next 32 bit data will written in next column and so on upto 8 column so all the 256 bit are written and
I am started to write next 256 bit from previous address 1 +8 and continuing the same
is this process is correct .
pls let me know if i am doing it wrong because in 1 Gb memory i cant wright even 3Mb data address is over folowing
06-10-2019 01:35 AM
Yes, you are writing correctly. However, usually we start to write to address 0, 8, and so on. Have you tried to read back the data you've written in the memory?
06-10-2019 01:49 AM
06-10-2019 02:03 AM
What's the frequency DDR3 interface is running at? The PHY to controller clock ratio is set to 4:1 in IP wizard?
For example, if the DDR3 is running at 400MHz and the PHY to controller clock ratio is set to 4:1, then the user interface should run at 100MHz. The user interface clock is generated by MIG IP.
06-10-2019 02:27 AM
06-11-2019 03:14 AM
For the clocking scheme, I suggest the system clock for DDR controller is directly from input FPGA pin. Please describe the failure phenomenon when you write/read at the user interface.
06-11-2019 07:43 PM
06-11-2019 11:29 PM
First run simulation first to check the user interface timing. If it's ok, insert ILA to capture the signals at the user interface. If you have problem problem simulation, you can run simulation with IP example design for comparison.
06-12-2019 01:59 AM