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Observer parithyila
Observer
426 Views
Registered: ‎04-09-2019

DDR 3 memory addresing

Hi ,

I am using kintex 7 FPGA , I  created  MIG for DDR 3 , I went for bank row column  memory mapping mode ,

I am having doubt in giving the address for this 

I am reading 256 bit data from fifo and writing at the address 1  (address is 29 bit through app_addr ) , I am writing the next data from address 8 and next data from previous address +8  is it the correct  way that i am to generating the address.

my assumption is address 1 will have 8 column which start from 0 to 7  so first 32 bit of 256 bit data will be written in column 0 next 32 bit data will written in next column and so on upto 8 column so all the 256 bit are written and 

I am started to write next 256 bit from previous address 1 +8 and continuing the same

is this process is correct .

 

pls let me know if i am doing it wrong because in 1 Gb memory i cant wright even 3Mb data address is over folowing

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9 Replies
Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎08-21-2007

回复: DDR 3 memory addresing

Yes, you are writing correctly. However, usually we start to write to address 0, 8, and so on. Have you tried to read back the data you've written in the memory?

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Observer parithyila
Observer
355 Views
Registered: ‎04-09-2019

回复: DDR 3 memory addresing

Hi I am facing some issue here ,I am using kintex 7 fpga series i connected clock to J20 pin 33 mhz as an input from that i am generating 100mhz system clock 200mhz reference clock and 80Mz for other logic i am using locked signal as an reset. the logic which uses 80Mhz are working fine , but ddr is not working. is there any solution
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Observer parithyila
Observer
351 Views
Registered: ‎04-09-2019

回复: DDR 3 memory addresing

calibration bit goes high
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Xilinx Employee
Xilinx Employee
350 Views
Registered: ‎08-21-2007

回复: DDR 3 memory addresing

What's the frequency DDR3 interface is running at? The PHY to controller clock ratio is set to 4:1 in IP wizard?

For example, if the DDR3 is running at 400MHz and the PHY to controller clock ratio is set to 4:1, then the user interface should run at 100MHz. The user interface clock is generated by MIG IP.

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Observer parithyila
Observer
342 Views
Registered: ‎04-09-2019

回复: DDR 3 memory addresing

our DDR3 is running at 400MHz and the PHY to controller clock ratio is set to 4:1 i am connecting 100 Mhz to the system clock and 200Mhz to the reference clock of Mig IP , both are derived from pll i am using no buffer option . and then the input clk and reset for the above mentioned pll is derived from another pll which takes the input from FPGA pin hi pls have a look on the single page sheet that i have attached . sry it an rough figure can u suggest me y this logic is not working .
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Xilinx Employee
Xilinx Employee
313 Views
Registered: ‎08-21-2007

回复: DDR 3 memory addresing

For the clocking scheme, I suggest the system clock for DDR controller is directly from input FPGA pin. Please describe the failure phenomenon when you write/read at the user interface. 

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Observer parithyila
Observer
301 Views
Registered: ‎04-09-2019

回复: DDR 3 memory addresing

Hi i can't connect the connect the direct fpga in to system clock because it is 33mhz so i am using a pll to get 100mhz ,200mhz system clk and reference clock, i am using a display to see the output but i cant see any thing on the display , and the current rate is also low. i am having a doubt in this clock architecture which i have given in the document.
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Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎08-21-2007

回复: DDR 3 memory addresing

First run simulation first to check the user interface timing. If it's ok, insert ILA to capture the signals at the user interface. If you have problem problem simulation, you can run simulation with IP example design for comparison.

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Observer parithyila
Observer
285 Views
Registered: ‎04-09-2019

回复: DDR 3 memory addresing

Hi,

Thanks for your reply as of now i am doing the same as you mentioned , i want to know can i generate clock for DDR module as i mentioned in the document. in the previous thread.i am also attaching here

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