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Contributor
Contributor
1,135 Views
Registered: ‎09-05-2014

DDR3 Artix750T Interface queries

Hello,

 

I'm trying to design a PCB with Artix 7 as a general purpose board for usage in physics experiments. I decided to use a 1GB RAM on board, and I'm using Micron MT41K1G8SN-125 for this. For connections between the RAM and FPGA, Xilinx MIG Guide suggests to use the IP core itself for getting the pins to which the RAM can be connected. So I used ISE 14.7 with Artix 100T 484 BGA package (as it is pin compatible with 50T 484 package) and created a custom RAM (using MT41K512M8 as base part and editing the number of address columns, as all other timing parameters from the data sheet were equal, Is this correct?) as the above part was not available. I set the clock speed in MIG to 3 ns (333.33 MHz) and MIG automatically selected 4:1 clock ratio. I use RZQ/6 (40 ohms) and RZQ/7 (34 ohms) for input and output termination resistances, and set the On chip termination on FPGA to 50 ohms (is this ok ?). The RAM operates at 1.35 V. And I have only this SRAM chip for interface.

 

I have the following doubts:

 

1. When the clock ratio is 4:1 does that mean my transfer rate will be 333.33*4 i.e. 1333 MT/s ?

2. Since the range of termination resistances are around 50 ohms, must I place a series termination resistance or simply using impedance match 50 ohm traces are sufficient to maintain signal integrity ? (I went through Micron's point to point design guide, but its a bit confusing).

3. Do I need a VTT ? I see some designs using 1 or 2 RAM chips not using termination to VTT.

4. Can I use the internal voltage reference on the FPGA itself ? Or must I use a external reference connected to VREF pins ? The MIG generator again said for Low speed transfers internal Vref would work. But what is optimal to use ?

5. On the x8 DDR RAM, there are two data strobes DQS and TDQS, where TDQS is shared with Data Mask. The data sheet says TDQS if enabled adds the same on die termination value to the balls to which it is conected. What is the actual purpose of TDQS? Must I use it or just leave it be ? My application is to just use the RAM as a large FIFO buffer if I have to store large volumes of data on the long run.

6. There are two clocks that have to be input to the MIG, the System clock and the reference clock for the IODELAYS. I'm planning to use a 100 MHz clock onboard. The  MIG generated a clock rate of 88.89 MHz for system clock. Must I also have separate crystals for the system and reference clocks or they can be generated from a PLL itself ? Because if I want to generate the 88.89 MHz clock from PLL, it may not be possible in the combinations of M/D I have explored.

 

I would be very grateful if someone can put me on the right track here ! 

 

Thank you!,

 

Mugundhan 

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5 Replies
Scholar dpaul24
Scholar
1,122 Views
Registered: ‎08-07-2014

Re: DDR3 Artix750T Interface queries

@mugundhaniia,

 

So I used ISE 14.7 with Artix 100T 484 BGA package

You are using Artix which is a series7 FPGA.

So you must use the latest version of Vivado (recommended is 2017.4) and not ISE.

Base your calculations as per Vivado results.

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Contributor
Contributor
1,079 Views
Registered: ‎09-05-2014

Re: DDR3 Artix750T Interface queries

Thank you dpaul24 ! I would appreciate guidance on other HW related queries as well ! especially regarding the terminations and the clocks !

 

I'll generate the pin-outs on Vivado 2017.4 too and verify the results !

 

-Mugundhan

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Explorer
Explorer
1,068 Views
Registered: ‎10-05-2010

Re: DDR3 Artix750T Interface queries


@mugundhaniiawrote:

6. There are two clocks that have to be input to the MIG, the System clock and the reference clock for the IODELAYS. I'm planning to use a 100 MHz clock onboard. The  MIG generated a clock rate of 88.89 MHz for system clock. Must I also have separate crystals for the system and reference clocks or they can be generated from a PLL itself ? Because if I want to generate the 88.89 MHz clock from PLL, it may not be possible in the combinations of M/D I have explored.


In a recent design, I used the on-board oscillator chip to provide the MIG  system clock (sys_clk_i), then used one of the MIG generated 'additional' clock outputs (ui_addn_clk_2) to provide the 200MHz reference clock, which connects to some sensor IODELAYs and the MIG clk_ref_i. 

 

---

Joe Samson

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Contributor
Contributor
1,053 Views
Registered: ‎09-05-2014

Re: DDR3 Artix750T Interface queries

Hi Joe,

 

Thanks for the clarification regarding the clock. As paul said I have generated the files in Vivado and the clock speeds are different ! will check out if these can be generated from my on board oscillator itself.

 

I think when you mean that you used the on-board oscillator, you used the on-board oscillator to generate the sys_clk signal through a PLL (?)

 

Thank you !

Mugundhan

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1,044 Views
Registered: ‎05-04-2018

Re: DDR3 Artix750T Interface queries


@mugundhaniiawrote:

I think when you mean that you used the on-board oscillator, you used the on-board oscillator to generate the sys_clk signal through a PLL (?)


No, the clock signal came into the FPGA from a clock pin, then connected to the MIG. I had a version using an Artix 35 where I ran the MIG using a clock from a PLL. This worked, but when I needed to add another PLL output, I ran into clock distribution problems and my best solution was to run the MIG directly from the FPGA input clock.

 

---

Joe 

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