UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor igork99456
Visitor
7,205 Views
Registered: ‎09-24-2012

DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Greetings.

 

MIG1.6 for 7 series (ISE 14.2); controller for DDR3 on Kintex-7 XC7K160T device; data bus width of 64 bits, and in 3 HP banks. The MIG has validated the UCF (so no pin placement problem does exist, AFAIK) and the boards are half-way through the layout already.

 

The design fails to pass PAR, and the message is as follows:

 

Place:1500 - The component inst_mig7_ik3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out belongs to a RPM (its structure is printed below) with 11 instances in the design, and there are only 8 suitable sites to place such RPMs in the device.

 

Of course as the message states, there are 11 instances of phaser_out and also I get this message 11 times. Also the RPM's structure is not printed anywhere. It does not make sense to me that 11 of those macros will not fit in this device, which has 32 PHASER_IN_PHY and 32 PHASER_OUT_PHY, out of which this DDR3 controller uses 8 and 11, respectively (usage details according to Planahead and/or Synthesis report). 

 

What can cause such an error, and what can be the possible solution?

 

I've seen AR #51914 ( http://www.xilinx.com/support/answers/51914.htm ) but clearly one can't go and change the LOC constraints for those RPMs without knowing what's inside?

 

Thanks in advance.

 

Igor

 

IK
0 Kudos
10 Replies
Xilinx Employee
Xilinx Employee
7,200 Views
Registered: ‎06-20-2008

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Please specify the package you are using. 

The tools are reporting that there are only 8 available PHASER_OUT_PHY in your.

This  makes me think that you are using the XC7K160T-1-FBG484 package which only has 2 HP banks bonded out.

If this is the package you are using then you will not have access to 3 HP banks so clarifying the package you are using might help us understand your error. 

 

The PHASER_OUT_PHY and PHASER_IN_PHY are associated with specific pins in the device so the fact that there are 32 available in the device that you have chosen, if they are not placed correctly, you will get the error you see.  This is why they are specifically located in the constraints file, they must get placed in a very specific location. 

0 Kudos
Visitor igork99456
Visitor
7,198 Views
Registered: ‎09-24-2012

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Hi

 

I'm using FFG676, according to UG475 v1.7 p.30 - "All HR and HP I/O banks and the GTX Quads are fully bonded out in these packages."

 

How can I derive the optimal placement of the pins out of the LOCs of the PHASERs? Where is the full list of needed constraints reside except for "example_top.ucf" / "example_top.pcf" ?

 

My current UCF file is almost 100% generated from the MIG, minor pins replacements were done, but all of them according to the rules in UG586, and afterwards the UCF was validated in MIG again, and there were no errors?

 

IK
0 Kudos
Xilinx Employee
Xilinx Employee
7,193 Views
Registered: ‎06-20-2008

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Yes in the package you are using all of the HP banks are bonded out.

So you should have 12 available PHASER_OUT_PHY that you can use, but still not all 32 in the device.

 

Without seeing your entire UCF it is difficult to understand whey the tools think there are only 8 of the available 12.

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
7,186 Views
Registered: ‎10-23-2007

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Suggestion: run the original example design from MIG through the tools and make sure it is okay.  Assuming it passes, then try your modifications in small batches.  Do note that the MIG tool will regenerate a new UCF and constraints based on your changes that you feed to it in the 'Update and Verify' process.  So you need to take the newly generated UCF for your design, not your hand modified version.

 

The phaser contsraints are not rocket science, but you do need to get a good physical picture of the device in order to understand them.  You can look at the FPGA editor to see where they are.  There are 4 pairs per bank (4 phaser_in and 4 phaser_out).  And you have to lock down the phasers corresponding to the physical pins you are using.

 

But there is no need whatsoever to do this manually.  The MIG tool should be doing all of it for you.  The above is really for background information.

 

0 Kudos
6,906 Views
Registered: ‎01-09-2013

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Hi, I have exactly the same problem you are describing here. Could you please let me know how you solved it? Thank you very much,

Matteo

 

0 Kudos
Visitor shenyy
Visitor
5,911 Views
Registered: ‎04-09-2014

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

first , check the .ucf file add you prj . if not ,the error maybe coming.    second  ,delete  chipscope  logic ,sometimes it will be ok.  

0 Kudos
2,751 Views
Registered: ‎05-07-2015

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Hi,

       I get the same problem ,can you tell me how you solve it?

 

     Thank you!

 

 

Tags (1)
0 Kudos
Xilinx Employee
Xilinx Employee
2,745 Views
Registered: ‎02-06-2013

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Hi

 

Do you see the error with the example design also and have you modified any Mig generated constraints.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Highlighted
2,740 Views
Registered: ‎05-07-2015

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Hi

    Do you meet the same question like 

ERROR:Place:1500 - The component
u_ddr3_ip/u_mig_7series_v1_7_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc
_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.d
dr_byte_lane_D/phaser_out belongs to a RPM (its structure is printed below)
with 11 instances in the design, and there are only 8 suitable sites to place
such RPMs in the device.
Comp

 

if you solve this question,please tell me.

 

Thank you very much.

0 Kudos
1,148 Views
Registered: ‎05-07-2015

Re: DDR3 / Kintex7: "Not enough suitable sites to place RPMs?" PAR error.

Hi

Folow the guide VC707-mig-pdf step by step,  when I map the design ,which totally produce by MIG。

The error apperance below:

Place:1500 - The component u_ddr3_ip/u_mig_7series_v1_7_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out belongs to a RPM (its structure is printed below) with 11 instances in the design, and there are only 8 suitable sites to place such RPMs in the device.

can you tell me how to solve it. I use the device xc7vx485t-2ffg1761,with ise14.3.

 

The part of ucf is below.

 

thank you

 

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y19;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y18;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y17;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y16;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y23;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y22;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y21;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y27;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y26;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y25;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y24;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y19;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y18;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y17;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y16;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y23;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y22;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y21;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y27;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y26;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y25;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y24;

 

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y19;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y18;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y17;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y16;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y23;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y22;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y21;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y27;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y26;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y25;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y24;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y19;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y18;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y17;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y16;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y27;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y26;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y25;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y24;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y4;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y6;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y4;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y6;


INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y243;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y231;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y219;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y207;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y343;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y331;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y319;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y307;

INST "u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y5;
INST "u_ddr3_infrastructure/mmcm_i" LOC=MMCME2_ADV_X1Y5;


NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK";
INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE";
INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES";
TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 1250 ps;
TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6;

INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC";
TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;

0 Kudos