UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Voyager
Voyager
118 Views
Registered: ‎08-16-2018

DDR3 routing, CK to DQS delay

I found in some Xilinx document:

CK/CK#  must arrive after DQS between 0 -1600 ps, recommended > 150 ps for components/ UDIMM and > 450 ps for RDIMM.

A delay of 150 ps represents something like 3 cm and that will apply to all Address and Control signals. This is not how existing boards are actually routed.

Incidentally, what would happen if CK is delayed by something in between 0 and 150 ps wrt DQS?

I also found the 7-Series MIG has something called PHASER_OUT to compensate for that. In that case, can I just use a delay > 0?

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
89 Views
Registered: ‎08-21-2007

回复: DDR3 routing, CK to DQS delay

Yes, you can. This ensure the MIG calibration can be completed successfully.

0 Kudos