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Adventurer
Adventurer
180 Views
Registered: ‎04-29-2018

DDR4 Calibration on multi controller design

I had a custom board based on zynq ultrascale+(xczu9eg-ffvc900-2i) FPGA. I choose to implement two DDR4 MIG's using Bank64 and Bank65.

Both the MIG's had independent external clocks(Si570) in their respective banks, and one sys_rst pin connected to both the MIG's. DDR4 reset_n's are coming from Bank66 for both the MIG's(separate reset pins unlike sys_rst)

I had 2 problems now,

1->Independently I am able to pass calibration on Bank64 but not on Bank65. Bank65 fails in the first stage

2->In another design, When i address both the MIG's together - Both of them fails calibration around stage10

Now i am not sure how to proceed on the debug, any pointer would be great. I thought back bone constraint not needed as there are 2 independent clocks

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3 Replies
Xilinx Employee
Xilinx Employee
148 Views
Registered: ‎03-04-2018

Re: DDR4 Calibration on multi controller design

Hello @trinadhkosuru ,

 

Could you please see a General Checks in the PG150(p.590) at first?

I have some comments.

-Did you try an example design?  That means there is only MIG in your design.

-Is the memory parts listed the MIG GUI(Micron parts)?  If not, you use the customer CSV.  Are value in the CSV correct?

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

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Adventurer
Adventurer
141 Views
Registered: ‎04-29-2018

Re: DDR4 Calibration on multi controller design

I will work on the general checks like you mentioned.

I haven't tried example design, but for the same device under test my current design works well on Bank64 and doesn't work on Bank65.

When i try to address both Bank64 and Bank65 together at same time, Calibration fails on both the Banks(MIG's). Was there some setting i need to do in FPGA or in constraints file

 

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Xilinx Employee
Xilinx Employee
123 Views
Registered: ‎08-21-2007

回复: DDR4 Calibration on multi controller design

I suggest you create IP example design which has only one controller and test it on board. That will help to identify whether the problem is related to hardward or not.

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