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DDR4 SODIMM pin swapping rules

Posts: 22
Registered: ‎10-03-2013

DDR4 SODIMM pin swapping rules

Hi all,


I need a clarification in the rules for pin swapping in the "Zynq UltraScale+ MPSoC Packaging and Pinouts" document:



According to Figure 2-1 and the text above it " Bits within a nibble must stay together". Is that rule valid only when we want to support write CRC?


According to the last rule "Bits within a byte lane can be swapped without restriction.". So these two rules are not aligned.


Can somebody explain me whether I can swap any bits in a byte lane or whether the bits within a nibble must stay together?




Xilinx Employee
Posts: 70
Registered: ‎10-19-2015

Re: DDR4 SODIMM pin swapping rules

Hi @iakovosmavro

The PS guidelines are confusing here. We are updating the user guide in the next release.


If you are not using the CRC function you are free to swap bits in a byte lane without restriction. 



Let me know if that is clear. 


Don’t forget to reply, kudo, and accept as solution.