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Participant johnmaclellan
Participant
234 Views
Registered: ‎11-30-2017

DDR4 memory with AXI interface not returning correct data

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I'm using a 512Mx16 DDR4 memory components. I use 4 devices to great a 64 bit wide data bus to the ddr4 components using the AXI user interface with a 512 bit data word.  I attached two pictures:  The write address and data to the DDR4.   The read address and data returned by the DDR4 memory.   I set arsize and awsize = 0x6, arcache and awcache=0x3.

100% of the time the first two 512 bit words are not returned by the memory.    I believe I'm sending the correct read address, the correct write address and wlen.

write.jpg
read.jpg
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1 Solution

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Participant johnmaclellan
Participant
149 Views
Registered: ‎11-30-2017

Re: DDR4 memory with AXI interface not returning correct data

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Upgraded Vivado from 2017 to 2018 and problem went away.

Thank you to everyone that replied.  I appreciate the help.

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5 Replies
Scholar dgisselq
Scholar
207 Views
Registered: ‎05-21-2015

Re: DDR4 memory with AXI interface not returning correct data

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@johnmaclellan,

Let me back you up a moment to your set up.  You said you are using four memory controllers, each presumably 128 bits wide, to create a 512 bit wide controller, right?  How are you merging these four controllers responses together?  Do they each have AXI interfaces?  When you make a request of your combined controller, are you waiting for all of the sub-controllers to acknowledge the request?

DDR SDRAM is a strange beast due the "dynamic" nature of the SDRAM.  This will cause the controller to take the SDRAM offline at regular intervals.  Further, given the nature of the asynchronous reset that typically starts these devices off, their offline intervals may not necessarily be synchronized.  Therefore, you can't ignore the handshaking signals of all but one of the sub-cores when creating a combined core.

From your simple note above, it's hard to tell if this is what you are doing or not, but it was my first guess as to what the problem might be.

Dan

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Participant johnmaclellan
Participant
196 Views
Registered: ‎11-30-2017

Re: DDR4 memory with AXI interface not returning correct data

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Sorry, I didn't explain the setup well.

There is only one DDR4 controller with a user interface data path width of 512 bits connect to four 512Mx16 DDR4 memories. (The ddr4 controller is set for a 64 bit word bus.)

I did catch one mistake from the previous pictures.   I was not holding wvalid high when wready was low.  That's fixed but I have the same result shown.

One other thing I found is the beginning of the data burst (not show in the read data picture) is coming out during a read cycle of an address space different than waddr.  Not sure what's going on?   The design meets all timing.

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Scholar watari
Scholar
186 Views
Registered: ‎06-16-2013

Re: DDR4 memory with AXI interface not returning correct data

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Hi @johnmaclellan 

 

I suggest you to make sure the followings.

 

1. Make sure Vref voltage.

2. Make sure connection of RESETN of DDR4.

3. Make sure the status of MIG. (ex. calibration and so on)

 

I guess it seems DRAM setting or PCB issue...

 

Best regards,

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Scholar dgisselq
Scholar
180 Views
Registered: ‎05-21-2015

Re: DDR4 memory with AXI interface not returning correct data

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@watarihas a good idea, perhaps it's start up related.  The MIG core produces it's own reset.  Are you using that for your design?  That reset will guarantee that your design doesn't start until all of the appropriate clocks are locked.

Dan

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Participant johnmaclellan
Participant
150 Views
Registered: ‎11-30-2017

Re: DDR4 memory with AXI interface not returning correct data

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Upgraded Vivado from 2017 to 2018 and problem went away.

Thank you to everyone that replied.  I appreciate the help.

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