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Observer seu_baikal
Observer
594 Views
Registered: ‎05-16-2018

How to connect four 16bit DDR3 to xc7a100tfgg676?

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Hello Xilinx expert

 Now,I'am design a xc7a100tfgg676 board,I want connect four 16bit DDR3 to FPGA,can I cont fly-by struct ,connect two DDR3's data on bank35,other two ddr3's data on bank 16,all four ddr3's  Address/control singal connect to bank34?

Every bank in 7 series can connect DDR3?QQ截图20180517000728.png

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Moderator
Moderator
866 Views
Registered: ‎11-28-2016

Re: How to connect four 16bit DDR3 to xc7a100tfgg676?

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Hello @seu_baikal,

 

Please look at the Design Guidelines section in UG586 starting on page 192.  There's a link to the latest version in my signature.

 

The MIG memory interfaces must be within the same I/O column and must be in contiguous banks.

Based on your description of the desired banks in the xc7a100tfgg676 device this is not going to be possible.

Please look at Figure 1-9 in UG475 for the xc7a100tfgg676 bank diagram and you'll see that going between banks 16, 34, and 34 the interface is not in contiguous banks nor is it in the same I/O column.

 

at100_banks.PNG

Here's a link to the latest version of UG475:

https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf

 

Additionally if you were to try this pin assignment in the MIG configuration GUI you would see that it is not valid.

3 Replies
Moderator
Moderator
867 Views
Registered: ‎11-28-2016

Re: How to connect four 16bit DDR3 to xc7a100tfgg676?

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Hello @seu_baikal,

 

Please look at the Design Guidelines section in UG586 starting on page 192.  There's a link to the latest version in my signature.

 

The MIG memory interfaces must be within the same I/O column and must be in contiguous banks.

Based on your description of the desired banks in the xc7a100tfgg676 device this is not going to be possible.

Please look at Figure 1-9 in UG475 for the xc7a100tfgg676 bank diagram and you'll see that going between banks 16, 34, and 34 the interface is not in contiguous banks nor is it in the same I/O column.

 

at100_banks.PNG

Here's a link to the latest version of UG475:

https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf

 

Additionally if you were to try this pin assignment in the MIG configuration GUI you would see that it is not valid.

Observer seu_baikal
Observer
564 Views
Registered: ‎05-16-2018

Re: How to connect four 16bit DDR3 to xc7a100tfgg676?

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thanks ryana
that's means i can use bank 13,14,15,16 to connect four ddr3?
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Moderator
Moderator
549 Views
Registered: ‎11-28-2016

Re: How to connect four 16bit DDR3 to xc7a100tfgg676?

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Hello @seu_baikal,

 

That's correct.  To get this interface to fit you'll need to use banks 13 through 16.

 

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