UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant andy_lvjing
Participant
467 Views
Registered: ‎03-26-2018

How to initialize the DDR4 via DDR4 core UI?

 I use the Vidado tool and generated a RDIMM IP , how could the host(FPGA) configure(write and read) the mode registers inside DDR4 SDRAM via the DDR CORE UI (APP_BUS)? 

The app_bus is the user interface between FPAG and DDR CORE. and it contain (app_addr[30:0]、app_cmd[2:0])、app_en、app_hi_pri、app_autoprecharge、app_wdf_data[511:0] ...) . the example pattern just write and read the RAM inside DDR4 SDRAM, not write and read mode registers inside DDR4 SDRAM. therefore, I do not which value shall I send to the app_bus. 

 

access_sdram_register.jpg
0 Kudos
1 Reply
Explorer
Explorer
425 Views
Registered: ‎03-31-2016

Re: How to initialize the DDR4 via DDR4 core UI?

You cannot.  The initialization/configuration is done automatically by the MIG core immediately after it comes out of reset and before init_calib_complete asserts.

 

The settings for the mode registers depend on the configuration entered when generating the MIG IP.