We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


MIG Clocking

Posts: 13
Registered: ‎02-14-2017

MIG Clocking


I am confused with the role and meaning of the many clocks available on the MIG.

There is: 

    1. sys_clk_i (input) 

    2. ui_clk (output)

    3. Clock Period (in the settings)

    4. PHY to Controller Clock Ratio (in the settings)

    5. Input Clock Period (in the settings)


Is someone able to clarify how those relate to each other and what their meaning is?

Posts: 5,664
Kudos: 793
Solutions: 1,017
Registered: ‎09-20-2012

Re: MIG Clocking

Hi @symm3try


clock period is the DDR3 memory clock period.

Input clock period is the system clock sys_clk period.

ui_clk is the MIG output clock whose frequency depends on PHY to controller clock ratio.


For more details refer to UG586 or below AR 



Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Posts: 9,049
Registered: ‎08-14-2007

Re: MIG Clocking

You didn't mention which device you're targetting, so I'll keep the responses general.  Note that there are differences between the MIG implementations for different FPGA families, including clocking and user interface.


sys_clk_i is the input clock driven by a board-level oscillator.  Its frequency provides the reference for the MMCM or PLL inside the MIG core to generate the necessary clocks.


ui_clk runs at the application interface frequency and is used for all command / address / data between MIG and the user application.  For 7-series MIG, its frequency is typically 1/4 of the clock going to the external memory devices.


Clock Period is the period of the clock driven to the memory devices.  So if you're running DDR3-800 (800 Mb/s) the clock frequency would be 400 MHz and "Clock Period" would therefore be 2500 ps.


PHY to Controller Clock Ratio describes the ratio of the memory chip clock to the user interface clock, and as I mentioned earlier is typically 4:1.  This ratio also determines the width of the data at the user interface, since the overall bandwidth must be maintained.


Input Clock Period is the period of sys_clk_i.  This is required to establish the parameters for the MMCM or PLL when generating the clocks for memory and user interface.

-- Gabor
Posts: 13
Registered: ‎02-14-2017

Re: MIG Clocking