02-13-2017 12:45 AM
I am doing a determination of a worst-case latency of my design. In my design there is a DDR3 memory controller with an AXI Interface. The only information I find regarding the latency of the DDR3 memory controller is the Answer Record 45644 (https://www.xilinx.com/support/answers/45644.html).
Are there more detailed information regarding calculating the latency of the controller? Or can I only use the simulation for determination of the worst-case latency of the DDR3 memory controller?
Thanks for helping!
02-13-2017 06:21 AM
There is no detailed doc with latency values.
You need to simulate the MIG core to determine the latency for your configuration and Memory access patterns.
02-13-2017 09:23 AM
maybe I am the only one, but to me this lack of information looks like a company is in early stage formation and not like a company more than two decades in business ...