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Explorer
Explorer
1,196 Views
Registered: ‎01-02-2012

MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Dear Xilinx-Experts!

we have a design with DDR3 SDRAM, using MIG successfully since at least 2 years. We know that all address & control signals must ideally be connected to the same bank. Our design has unfortunately a little exception there: ddr3_reset_n is on Bank-15, although all other address & control signals are on Bank-14. MIG v4.1 (@Vivado 2018.2) GUI has no problem validating this pin-out. Since the reset signal is not timing critical, we did not have any problem with the hardware either. 

After upgrading to MIG v4.2 (@Vivado 2018.3), I get the error shown below. Mentioned AR is from 2013 and there is no workaround there to pass the pin-out validation!?

image.png

By the way, we are using custom memory component within the MIG and the automatic IP upgrade at Vivado 2018.3 could not do the conversion properly: Custom part had to be redefined. However, redefining the custom part did not help either.
It is lost after output product's regeneration. This seems to be even worse! I could modify the pin-out in *.prj files. 

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Moderator
Moderator
665 Views
Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @xil_azdem,

The Answer Record including a patch is now public and can be found here: https://www.xilinx.com/support/answers/71898.html. The issue will be natively fixed in the next major release of Vivado.

Please mark this response as a solution so we can distribute the patch more thoroughly on the forums.

Thanks,
Cory

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13 Replies
Moderator
Moderator
1,128 Views
Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @xil_azdem,

Could you please provide your 2018.2 XCI/PRJ that is working so I can run some testing in 2018.3?

Thanks,
Cory

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Visitor vkampen
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Registered: ‎12-27-2018

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello all,

Same issue here. Upgrading from 2018.2.2 to 2018.3 threw an 'DRC validation' error, referring to the (2013) AR#43481. The design was obviously unchanged from 2018.2.2 (that I upgraded because of https://forums.xilinx.com/t5/Simulation-and-Verification/after-2018-2-1-to-2018-2-2-Vivado-updating-simulations-fails/td-p/898062). Similarly, instantiating the MIG using the UCF file attached works in 2018.2.2, but fails in 2018.3.

Attached the pin-out. DDR3 settings as in https://docs.opalkelly.com/display/XEM7320/DDR3+Memory. 

Can you please fix this (and don't break anything in the process...)?

Best regards,

Maarten van Kampen

 

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Moderator
Moderator
979 Views
Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @vkampen, @xil_azdem

I have been able to reproduce the issue using @vkampen's UCF / DDR3 configuration. I am working on putting together an Answer Record to provide you with a solution. Please give me some time to get it approved.

Thanks,
Cory

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Moderator
Moderator
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Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @xil_azdem, @vkampen,

I have sent both of you an EZMOVE package including a 2018.3 patch. After you unzip the attachment, please take a quick peek at the readme. It explains 3 different install methods. Pick the one that works for your setup.

Let me know if you have any other issues.

Cory

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Explorer
Explorer
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Registered: ‎01-02-2012

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hi @coryb,

Thanks for the patch!

Does it fix the both issues mentioned above or only the custom part issue?

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Moderator
Moderator
835 Views
Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @xil_azdem,

The patch fixes both issues. The patch allows custom parts to be maintained during the upgrade process to Vivado 2018.3. And it also allows custom parts with previously validated pinouts to continue to validate in 2018.3.

Thanks,
Cory

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Visitor vkampen
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Registered: ‎12-27-2018

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello Coryb,

The patch allows me to successfully create a new project with a MIG with the desired pin-out. The patched 2018.3 can also upgrade an existing project (though at least one project caused a silent crash). The upgraded project then has outdated IP. I can upgrade all IP, except the existing MIG. Vivado silently crashes (disappears) when trying to upgrade the MIG. Did not yet try to delete the MIG in an upgraded project and replace it with a new one. I guess this should work and be a work-around.

Best regards,

Maarten

ps. attached a not very enlightening screenshot of vivado upgrading my MIG; in a previous run it upgraded the earlier IP up to the MIG and crashed. Upon restarting an reopening, only two IPs remain outdated. Selecting only the MIG and pressing 'update' causes a silent crash. Which is obviously not visible :-).

screenshot.png
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Observer driss
Observer
748 Views
Registered: ‎05-13-2018

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello Coryb,

We have the same bug pin-out MIG validation after upgrading to Vivado 2018.3.

Best regards,

Driss

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Moderator
Moderator
730 Views
Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @vkampen,

Which version of Windows 10 are you using specifically?

Thanks,
Cory

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Visitor vkampen
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Registered: ‎12-27-2018

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello Corry,

Wrt windows version: see screenshot attached. 

Wrt IP upgrade issues: I now suspect I may be using your tools 'wrong'. I have the habit of making some part of the required functionallity work (e.g. transfer through DDR3 FIFO, but with random data), then copy the project and add functionallity (e.g. an ADC that generates useful data). I now see that the project that has the MIG inserted that upgrade. But the 2nd one does not. To upgrade I copy the project to a new folder (and even drive). And the errors (when it gives errors) refer to the folder name of the 1st project. So it may be that some IP uses absolute paths or non-project relative paths that fail when copying projects (?).

Forgotten in the previous post: thanks for providing the patch, very helpful already in its current stage. Will move to 2018.3.

Best regards,

Maarten

 

Errors/warning upgrading MIG 4.1 to MIG 4.2. Project successfully synthesized in 2018.2. The project being upgraded was "d:\temp\RAMADC - speedtest", based on a project "RAMADC". The errors seem to refer to the original project that I copied.

"

  • [#UNDEF] Error in opening fpga xml file D:/Temp/RAMADC
  • [#UNDEF] Error in opening fpga xml file D:/Temp/RAMADC
  • [IP_Flow 19-3475] Tcl error in ::ipgui_ddr3_ram::updateAllModelParams procedure for IP 'ddr3_ram'. ERROR: [Common 17-39] 'mig7series_init' failed due to earlier errors.
  • [xilinx.com:ip:mig_7series:4.2-0] ddr3_ram: Code generation aborted: Unconfigured MIG instance
  • [IP_Flow 19-167] Failed to deliver one or more file(s).
  • [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'ddr3_ram'. Failed to generate 'Verilog Instantiation Template' outputs:
  • [IP_Flow 19-3408] Upgrade of ddr3_ram from Memory Interface Generator (MIG 7 Series) 4.1 to Memory Interface Generator (MIG 7 Series) 4.2 has resulted in an incomplete parameterization. Please review the message log, and recustomize this instance before continuing with your design.
  • [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2018.3/data/ip/xilinx/mig_7series_v4_2/xit/instantiation_template.xit':
  • [Coretcl 2-1279] The upgrade of 'ddr3_ram' has identified issues that may require user intervention. Please review the upgrade log 'd:/Temp/RAMADC - speedtest/ip_upgrade.log', and verify that the upgraded IP is correctly configured.
  • "
winver.PNG
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Moderator
Moderator
723 Views
Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @vkampen,

Please remove the space for your project name and then try upgrading. I don't think Vivado plays well with spaces in the project name.

Thanks,
Cory

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Visitor vkampen
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Registered: ‎12-27-2018

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello Cory,

Thanks for spotting, indeed removing the space fixes the upgrade issues / silent crashes. That than leaves (for me) a fully working patch.

It is definitely not the first time I fell in the 'space in the path' trap. Probably also not the last time. I guess you consider it 'user error'. From my perspective the 'space in path' limitation it is a neat way to increase the learning curve a bit... 

Best regards,

Maarten

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Moderator
Moderator
666 Views
Registered: ‎02-11-2014

Re: MIG v4.2 (@Vivado 2018.3) pin-out validation is too strict & custom part support is gone!

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Hello @xil_azdem,

The Answer Record including a patch is now public and can be found here: https://www.xilinx.com/support/answers/71898.html. The issue will be natively fixed in the next major release of Vivado.

Please mark this response as a solution so we can distribute the patch more thoroughly on the forums.

Thanks,
Cory

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