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Observer j0n
Observer
286 Views
Registered: ‎09-28-2017

Not seeing the correct frequency value for ui_clk in MIG7

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Hi all, 

According to UG587, ui_clk must be a half or quarter of the DRAM clock. I set my MIG to use 2:1 PHY to Controller Clock Ratio so I was expecting half the DRAM clock. 
When going through the design schematic generated by Vivado I see a different value. Below is step by step how I calculate this wrong value. 

sys_clk is set to 200.763 MHz and memory clock period is set to 326.26 MHz in the MIG wizard. 
These are the attribute parameters generated by the MIG: 

  CLKIN_PERIOD          : integer := 4981;
                                     -- Input Clock Period
   CLKFBOUT_MULT         : integer := 13;
                                     -- write PLL VCO multiplier
   DIVCLK_DIVIDE         : integer := 2;
                                     -- write PLL VCO divisor
   CLKOUT0_PHASE         : real    := 0.0;
                                     -- Phase for PLL output clock (CLKOUT0)
   CLKOUT0_DIVIDE        : integer := 2;
                                     -- VCO output divisor for PLL output clock (CLKOUT0)
   CLKOUT1_DIVIDE        : integer := 4;
                                     -- VCO output divisor for PLL output clock (CLKOUT1)
   CLKOUT2_DIVIDE        : integer := 64;
                                     -- VCO output divisor for PLL output clock (CLKOUT2)
   CLKOUT3_DIVIDE        : integer := 8;
                                     -- VCO output divisor for PLL output clock (CLKOUT3)
   MMCM_VCO              : integer := 652;
                                     -- Max Freq (MHz) of MMCM VCO
   MMCM_MULT_F           : integer := 4;
                                     -- write MMCM VCO multiplier
   MMCM_DIVCLK_DIVIDE    : integer := 1;
                                     -- write MMCM VCO divisor

First, these are the calculations for the PLLE2 output clocks. They seem correct to me: 

freq_refclk = (sys_clk * CLKFBOUT_MULT) / (DIVCLK_DIVIDE * CLKOUT0_DIVIDE) => (200.763 * 13) / (2 * 2 )= 652.47 MHz 
mem_refclk (sys_clk * CLKFBOUT_MULT) / (DIVCLK_DIVIDE * CLKOUT1_DIVIDE) => (200.763 * 13) / (2 * 4 ) = 326.24 MHz

UG587 says mem_refclk and freq_refclk must have the same frequency. I assume this is the case here since mem_refclk is DDR so 326.24 * 2 = 652.47 MHz which is what I expect.

Anyway, CLKOUT3 of the PLLE2 connects to the primary clock input of the MMCME2 which in turn generates the ui_clk (this is where I see the problem). 

Again from the PLLE2, 
CLKOUT3 = (sys_clk * CLKFBOUT_MULT) / (DIVCLK_DIVIDE * CLKOUT3_DIVIDE) => (200.763 * 13) / (2 * 8 ) = 163.11 MHz (This goes to MMCM's CLKIN1) 

Now as for the MMCM,
CLKIN1 = 163.11 MHz. 
If I follow the signals in the schematic, CLKFBOUT is my ui_clk. When I calculate this value, 

CLKFBOUT = ( CLKIN1 *  MMCM_MULT_F ) / MMCM_DIVCLK_DIVIDE  => 163.11 * 4 / 1= 652.47 MHz. This is the same value for my mem_refclk and I think this should be half this value according to UG587. 

Hopefully someone can point me out in the right direction of what I am doing wrong.  




 

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Moderator
Moderator
234 Views
Registered: ‎11-28-2016

Re: Not seeing the correct frequency value for ui_clk in MIG7

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Hello @j0n,

The ui_clk is always 1:2 or 1:4 the DDR interface clock.  This is an internally generated clock based on your MIG configuration.

The sys_clk is an external clock that's used by the MIG IP to generate the rest of the clocks required to run the IP, and it supports a wide range of values due to the flexibility of being manipulated by a PLL.

Once you set the "Clock Period" for the DDR3 memory interface rate and the "PHY to Controller Clock Ratio" on the "Controller Options" page of the MIG GUI the available "Input Clock Period" options for your sys_clk appear on the next page.  After that the tools handle the rest.  Unless the IP is being manually modified then the tools are absolutely generating the correct settings and clock values based on the way you configured the core.

4 Replies
Moderator
Moderator
235 Views
Registered: ‎11-28-2016

Re: Not seeing the correct frequency value for ui_clk in MIG7

Jump to solution

Hello @j0n,

The ui_clk is always 1:2 or 1:4 the DDR interface clock.  This is an internally generated clock based on your MIG configuration.

The sys_clk is an external clock that's used by the MIG IP to generate the rest of the clocks required to run the IP, and it supports a wide range of values due to the flexibility of being manipulated by a PLL.

Once you set the "Clock Period" for the DDR3 memory interface rate and the "PHY to Controller Clock Ratio" on the "Controller Options" page of the MIG GUI the available "Input Clock Period" options for your sys_clk appear on the next page.  After that the tools handle the rest.  Unless the IP is being manually modified then the tools are absolutely generating the correct settings and clock values based on the way you configured the core.

Voyager
Voyager
218 Views
Registered: ‎02-01-2013

Re: Not seeing the correct frequency value for ui_clk in MIG7

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4:1 is the 'normal' operating rate for DDR3 MIG. 2:1 is the 'turbo' rate that's only available for DDR interfaces that are running relatively slow, since the necessarily faster clocks needed to run in 2:1 mode can bump into the ceilings of FPGA operating limits.

4:1 means that the internal clock runs at 1/4 the rate of the memory clock. On each internal clock, 8 bits of data are moved per DDR3 DQ pin. 8 = 4 x 2. The '4' of that equation is due to the clock ratio, the '2' is because of the double-data-rate nature of the interface.

See? I'm not making this up...

2019-01-18_17-03-12.jpg

Your memory clock is running at 326 MHz. Your data rate is 652 Mbps. The internal clock of a 4:1 MIG controlling your interface would be running at 81.5 MHz. 

You're running in 2:1 mode, so your internal clock should be double that, or 163 MHz.

Notwithstanding any misapprehensions you had coming into this, all appears to be well.

-Joe G.

 

 

 

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Voyager
Voyager
214 Views
Registered: ‎02-01-2013

Re: Not seeing the correct frequency value for ui_clk in MIG7

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P.S. If, for fun, you re-generate your MIG in 4:1 mode, you'll find that MMCM_MULT_F changes to 8, from 4.

Observer j0n
Observer
170 Views
Registered: ‎09-28-2017

Re: Not seeing the correct frequency value for ui_clk in MIG7

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Hi @ryana and @jg_bds,

Apologies for the late reply, was not on the forum the past weekend. 
I understand what you are telling me about the ui_clk always being 1:2 or 1:4 the DDR clock. I was able to simulate the MIG design and indeed I see the ui_clk with the correct frequency in both 1:2 and 1:4 mode. 
I guess I was more concerned when checking the MIG source code with the PLL and MMCM parameters I was not able to calculate the expected frequency (as shown in my initial post). But yeah, I think I can put this to rest knowing the MIG is doing it's job properly. Thanks. 

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