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QDRII- caib_done not asserted

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Adventurer
Posts: 86
Registered: ‎11-22-2016

QDRII- caib_done not asserted

Hi,

Working on a custom board with 144bit Cypress QDRII connected to virtex7(485t) FPGA. Generated a VHDL example design to test this interface using vivado 2016.4. The qdr2 memory controller has been configured with 400MHz clock(to drive qdr2 memory) and receives an input clock of 200MHz.

The captured ILA signals show that calib_done is not asserted and the debug_phy_status reads 0x16. Attaching the ila dump for reference. I would appreciate any help in understanding the issue for failure.

Adventurer
Posts: 86
Registered: ‎11-22-2016

Re: QDRII- caib_done not asserted

Please find the attached screen shots of the ILA.

 

Regards,

Manoj

 

ila_data1.png
ila_data2.png
Xilinx Employee
Posts: 39
Registered: ‎10-19-2015

Re: QDRII- caib_done not asserted

Hi @manoj_xilinx

 

The QDR IP is fairly sensitive to trace skews and clock jitter. Can you show me how you incorporated the FPGAs package delays into your overall trace delay calculations? 

Can you show me all your trace lengths for the write data path? 

Do you have your system input clock in the same IO column as the data bits? 

Please confirm that you have not modified the IP in any way. If you have, let me know what the modifications are as most of the time any modification to the IP will cause reliability issues during calibration. 

 

Thanks,

Matt 

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Adventurer
Posts: 86
Registered: ‎11-22-2016

Re: QDRII- caib_done not asserted

Hi Matt,

 

Sorry for the delay.

 

To answer your query,

 

The system input clock is not connected to the IO column which has data bits.

There is no modification to QDR IP core. The generated Example design has been used without any modifications.

Please find the trace length for write data path below,

Net name                                      Total legnth(mils)

VIRTEX_QDR2_MEM1_D0           1670.64
VIRTEX_QDR2_MEM1_D1           1670.38
VIRTEX_QDR2_MEM1_D2           1669.63
VIRTEX_QDR2_MEM1_D3           1672.06
VIRTEX_QDR2_MEM1_D4           1670.59
VIRTEX_QDR2_MEM1_D5           1671.51
VIRTEX_QDR2_MEM1_D6           1670.56
VIRTEX_QDR2_MEM1_D7           1668.27
VIRTEX_QDR2_MEM1_D8           1671.2
VIRTEX_QDR2_MEM1_D9           1669.81
VIRTEX_QDR2_MEM1_D10         1671.31
VIRTEX_QDR2_MEM1_D11         1669.61
VIRTEX_QDR2_MEM1_D12         1671.18
VIRTEX_QDR2_MEM1_D13         1669.69
VIRTEX_QDR2_MEM1_D14         1669.38
VIRTEX_QDR2_MEM1_D15         1669.6
VIRTEX_QDR2_MEM1_D16         1670.23
VIRTEX_QDR2_MEM1_D17         1669.24
VIRTEX_QDR2_MEM1_D18         1675.12
VIRTEX_QDR2_MEM1_D19         1674.31
VIRTEX_QDR2_MEM1_D20         1674.93
VIRTEX_QDR2_MEM1_D21         1673.2
VIRTEX_QDR2_MEM1_D22         1672.07
VIRTEX_QDR2_MEM1_D23         1674.04
VIRTEX_QDR2_MEM1_D24         1670.93
VIRTEX_QDR2_MEM1_D25         1673.23
VIRTEX_QDR2_MEM1_D26         1672.12
VIRTEX_QDR2_MEM1_D27         1672.33
VIRTEX_QDR2_MEM1_D28         1672.31
VIRTEX_QDR2_MEM1_D29         1670.18
VIRTEX_QDR2_MEM1_D30         1670.23
VIRTEX_QDR2_MEM1_D31         1674.94
VIRTEX_QDR2_MEM1_D32         1673.33
VIRTEX_QDR2_MEM1_D33         1693.63
VIRTEX_QDR2_MEM1_D34         1671.62
VIRTEX_QDR2_MEM1_D35         1672.72

 

Kindly let me know for further clarifications.

 

Regards,jagadish

 

Xilinx Employee
Posts: 39
Registered: ‎10-19-2015

Re: QDRII- caib_done not asserted

Hi @manoj_xilinx

 

sorry for the delay getting back to you, if you don't @ me I won't get a notification... :( 

 

The Max trace length provided is 1693.63 (mils?) and the min trace length provided is 1668.27 (mils?) 

 

Do these trace lengths include the package delay provided by Vivado if you use the TCL command write_csv <file_name> on either a synthesized or implemented design? The FPGA will not deskew the package delays for you so you need to do that in the trace routing. 

 

 

Do you have the read path trace lengths and the address trace lengths as well?

 

Regards,

Matt 

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Adventurer
Posts: 86
Registered: ‎11-22-2016

Re: QDRII- caib_done not asserted

[ Edited ]

Hi @mcertosi,

 

Actually we have not taken the package delay into account for routing.

 

Please find the read and address trace length below,

 

Read trace length(mils)
VIRTEX_QDR2_MEM1_Q0   1671.14
VIRTEX_QDR2_MEM1_Q1   1669.19
VIRTEX_QDR2_MEM1_Q2   1669.21
VIRTEX_QDR2_MEM1_Q3   1669.36
VIRTEX_QDR2_MEM1_Q4   1669.78
VIRTEX_QDR2_MEM1_Q5   1668.92
VIRTEX_QDR2_MEM1_Q6   1670.94
VIRTEX_QDR2_MEM1_Q7   1669.27
VIRTEX_QDR2_MEM1_Q8   1670.91
VIRTEX_QDR2_MEM1_Q9   1668.93
VIRTEX_QDR2_MEM1_Q10  1669.23
VIRTEX_QDR2_MEM1_Q11  1671.02
VIRTEX_QDR2_MEM1_Q12  1671.03
VIRTEX_QDR2_MEM1_Q13  1669.85
VIRTEX_QDR2_MEM1_Q14  1669.12
VIRTEX_QDR2_MEM1_Q15  1668.17
VIRTEX_QDR2_MEM1_Q16  1669.67
VIRTEX_QDR2_MEM1_Q17  1670.86
VIRTEX_QDR2_MEM1_Q18  1784.81
VIRTEX_QDR2_MEM1_Q19  1789.87
VIRTEX_QDR2_MEM1_Q20  1784.68
VIRTEX_QDR2_MEM1_Q21  1790.74
VIRTEX_QDR2_MEM1_Q22  1783.39
VIRTEX_QDR2_MEM1_Q23  1782.73
VIRTEX_QDR2_MEM1_Q24  1779.5
VIRTEX_QDR2_MEM1_Q25  1784.77
VIRTEX_QDR2_MEM1_Q26  1782.45
VIRTEX_QDR2_MEM1_Q27  1786.51
VIRTEX_QDR2_MEM1_Q28  1790.21
VIRTEX_QDR2_MEM1_Q29  1784.32
VIRTEX_QDR2_MEM1_Q30  1786.21
VIRTEX_QDR2_MEM1_Q31  1788.92
VIRTEX_QDR2_MEM1_Q32  1780.52
VIRTEX_QDR2_MEM1_Q33  1781.73
VIRTEX_QDR2_MEM1_Q34  1783.5
VIRTEX_QDR2_MEM1_Q35  1792.19

Address Trace Length(mils) 
VIRTEX_QDR2_MEM1_A1    1487.67
VIRTEX_QDR2_MEM1_A2    1485.61
VIRTEX_QDR2_MEM1_A3    1488.39
VIRTEX_QDR2_MEM1_A4    1488.49
VIRTEX_QDR2_MEM1_A5    1484.53
VIRTEX_QDR2_MEM1_A6    1486.34
VIRTEX_QDR2_MEM1_A7    1485.67
VIRTEX_QDR2_MEM1_A8    1485.84
VIRTEX_QDR2_MEM1_A9    1487.37
VIRTEX_QDR2_MEM1_A10  1487.66
VIRTEX_QDR2_MEM1_A11  1481.48
VIRTEX_QDR2_MEM1_A12  1488.94
VIRTEX_QDR2_MEM1_A13  1485.09
VIRTEX_QDR2_MEM1_A14  1488.44
VIRTEX_QDR2_MEM1_A15  1490.3
VIRTEX_QDR2_MEM1_A16  1488.19
VIRTEX_QDR2_MEM1_A17  1489.81
VIRTEX_QDR2_MEM1_A18  1486.24
VIRTEX_QDR2_MEM1_A19  1488.74
VIRTEX_QDR2_MEM1_A20  1488.11
VIRTEX_QDR2_MEM1_A21  1488.25

VIRTEX_QDR2_MEM1_BWS0    1488.31
VIRTEX_QDR2_MEM1_BWS1    1489.65
VIRTEX_QDR2_MEM1_CQ_P0  1488.62
VIRTEX_QDR2_MEM1_CQ_N0  1481.42
VIRTEX_QDR2_MEM1_K_P0     1489.05
VIRTEX_QDR2_MEM1_K_N0     1487.11
VIRTEX_QDR2_MEM1_RPS#     1484.48
VIRTEX_QDR2_MEM1_WPS#    1482.89

 

Regards,

Manoj

Xilinx Employee
Posts: 39
Registered: ‎10-19-2015

Re: QDRII- caib_done not asserted

Hi @manoj_xilinx

 

Not accounting for the FPGA package delay is likely the root cause of this failure. 

The maximum electrical delay between any bit in the data bus, D, and it's associated K/K# clk should be 15pS

The maximum electrical delay between any bit in the data bus, Q, and it's associated CQ/CQ# should be 15pS

The maximum electrical delay between any address and control signals and corresponding K/K# should be 50pS

There isn't a spec for CK and K clocks.

 

I believe once you get the pin delays at add them to your trace lengths you'll find the electrical delay of each trace in the group does not match the quoted requirement. 

 

We can continue the exercise in this thread. Please use the FPGA pin delays, the pin out for your QDR interface, and the dielectric constant of your PCB material and use them to calculate the total electrical delay for each net. 

 

Regards,

Matt 

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Don’t forget to reply, kudo, and accept as solution.
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Adventurer
Posts: 86
Registered: ‎11-22-2016

Re: QDRII- caib_done not asserted

Hi Matt,

 

Thanks for your response.

 

As per your recommendation, we have calculated the delay and found a difference of 28pS  between data bus D and its associated clock. If this is the cause for failure, can there be a work around to access QDR.

 

 

Regards,

Manoj  

Xilinx Employee
Posts: 39
Registered: ‎10-19-2015

Re: QDRII- caib_done not asserted

Hi @manoj_xilinx

You can try running the interface as slow as possible and seeing if that works. You can then slowly increase the configured clock frequency and retest until you've reached your system's FMAX. 

If nothing works, you'll want to respin the board taking the FPGA package delays into account. At that point, it would be good practice to move the input clock into the same IO bank column as the QDR IO bits. 

Regards,

Matt 

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Don’t forget to reply, kudo, and accept as solution.
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