10-12-2017 06:02 AM
Working on a custom board with 144bit Cypress QDRII connected to virtex7(485t) FPGA. Generated a VHDL example design to test this interface using vivado 2016.4. The qdr2 memory controller has been configured with 400MHz clock(to drive qdr2 memory) and receives an input clock of 200MHz.
The captured ILA signals show that calib_done is not asserted and the debug_phy_status reads 0x16. Attaching the ila dump for reference. I would appreciate any help in understanding the issue for failure.