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Spartan 6 MIG (control DDR3) write Read Data mismatch problem

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Observer
Posts: 26
Registered: ‎06-30-2011

Spartan 6 MIG (control DDR3) write Read Data mismatch problem

[ Edited ]

FPGA : Spartan 6, XC6SLX75, FGG484-3

DDR3 : SDRAM 2Gbit(Micro, MT41K128M16JT125-K)

 

Settings for MIG as follow

//==========================================

 

/*******************************************************/

/* Controller 3 */

/*******************************************************/

Controller Options :

Memory : DDR3_SDRAM

Interface : AXI

Design Clock Frequency : 3000 ps (333.33 MHz)

Memory Type : Components

Memory Part : MT41J128M16XX-125

Equivalent Part(s) : MT41J128M16HA-125

Row Address : 14

Column Address : 10

Bank Address : 3

Data Mask : enabled

 

Memory Options :

Burst Length : 8(00)

CAS Latency : 6

TDQS enable : Disabled

DLL Enable : Enable

Write Leveling Enable : Disabled

Output Drive Strength : RZQ/6

Additive Latency (AL) : 0

RTT (nominal) - ODT : RZQ/4

Auto Self Refresh : Enabled

CAS write latency : 5

Partial-Array Self Refresh : Full Array

High Temparature Self Refresh Rate : Normal

 

User Interface Parameters :

Configuration Type : Two 32-bit bi-directional and four 32-bit unidirectional ports

Ports Selected : Port0

Memory Address Mapping : BANK_ROW_COLUMN

 

Arbitration Algorithm : Round Robin

 

Arbitration :

Time Slot0 : 0

Time Slot1 : 0

Time Slot2 : 0

Time Slot3 : 0

Time Slot4 : 0

Time Slot5 : 0

Time Slot6 : 0

Time Slot7 : 0

Time Slot8 : 0

Time Slot9 : 0

Time Slot10: 0

Time Slot11: 0

 

FPGA Options :

Class for Address and Control : II

Class for Data : II

Memory Interface Pin Termination : CALIB_TERM

DQ/DQS : 25 Ohms

Bypass Calibration : enabled

Debug Signals for Memory Controller : Disable

Input Clock Type : Single-Ended

//==========================================

 

my Memory control structure is like below

 

Memory control structure.png

 

I got some problem, when access DDR3, Data mismatch issue. I use chipscope to monitor WATA and RDATA.

 

 

AXI signals when write and read DDR

 

write data to DDR3

AXI signals_write.png

 

Read from DDR3

AXI signals_read.png

 

When comparing WDATA and RDATA, it is mismatch, error happen.

WDATA_1.png

 

RDATA_1.png

 

But the weird part is, if I write data Full of 0xDDDD, or 0xFFFF, I can read 100% correct data back

 

Even if I write data like below, I still can get correct result. inside RED line is the data I write to DDR

ST_pattern.png

 

What I find out is, error happens when writing certain kind of data into memory. Nothing to do with memory location. Any memory location can repeat above error as long as you write into certain kind of data pattern.

 

From Chipscope, WDATA is totally correct before into MIG. But goes wrong after MIG(RDATA)

 

I will very like to hear any suggestion, because I've been trapped for very long time(couple of months).

 

Thank you

 

 

 

 

Observer
Posts: 26
Registered: ‎06-30-2011

Re: Spartan 6 MIG (control DDR3) write Read Data mismatch problem

From document, SP605

 

Using PULL UP resistor 49.9 ohm for Address bus, 100 ohm between CLK_P and CLK_N, like below

DDR_pull up R.png

 

What I used on DDR address bus is 33 ohm, and 82 ohm between CLK_P and CLK_N

 

Do I need to change resistors ?