UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor norn
Visitor
898 Views
Registered: ‎01-03-2018

UltraScale DDR4 Clamshell

Jump to solution

Hi!

In UG583 v1.11,Figure2-24 shows a Clamshell topology which needs to change layer up and down. In my application,there are 9 DDR4 SDRAMs speed at 2666Mbps,and only 4 inner layers can be routing signals.I cannot fanout to route like Clamshell. Can I route Address/Control/Command signals in a single layer from the first to the last SDRAM,as the red line shown in my picture?

05ECDB4A-DFA9-4DC5-8132-A319B87995D5.jpeg

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
1,105 Views
Registered: ‎11-28-2016

Re: UltraScale DDR4 Clamshell

Jump to solution

Hello @norn,

 

It is possible to route the address/command bus in the way you depicted but you will have issues with signal integrity from the long stubs going to the memory devices on the bottom layer.  These stubs will cause a lot of ringback in the design, especially at the first few DRAM placements.  I have seen a few designs that tried this method and it is extremely challenging to get a stable solution.  Extensive simulations must be done on the interface and you must adhere to all the other guidelines in UG583.  At 2666Mbps the margin for error is small so the layout must be as robust as possible in all other areas.

1 Reply
Moderator
Moderator
1,106 Views
Registered: ‎11-28-2016

Re: UltraScale DDR4 Clamshell

Jump to solution

Hello @norn,

 

It is possible to route the address/command bus in the way you depicted but you will have issues with signal integrity from the long stubs going to the memory devices on the bottom layer.  These stubs will cause a lot of ringback in the design, especially at the first few DRAM placements.  I have seen a few designs that tried this method and it is extremely challenging to get a stable solution.  Extensive simulations must be done on the interface and you must adhere to all the other guidelines in UG583.  At 2666Mbps the margin for error is small so the layout must be as robust as possible in all other areas.