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Visitor iamay88
Visitor
600 Views
Registered: ‎12-13-2017

Ultrascal MIG Self Refresh mode

Hi.

 

I have some question about Self Refresh Operation with DDR4 MIG ultrascale v.2.2.

If there is no reconfiguration with any other bitstream, can I skip to Save and Restore XSDB BRAM?

I checked the RESET_n and CKE signal by Simulation result and ILA, there was no change during Self Refresh.

For this reason, I think it is possible to skip Save and Restore XSDB BRAM during Self Entry and Exit.

I want to make sure about this.

 

And I think there is DRAM Spec. violation during Self Exit operation with DDR4 MIG ultrascale v2.2.

Refer to the DDR4 DRAM Spec. the clock must be stable prior to CKE going back HIGH.

However, the CK starts toggle after CKE HIGH. (Also I checked the simulation result and ILA.)

Isn't the Spec. violation?

Is it okay to operate DRAM normally after Self Exit?

 

Thanks.

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1 Reply
Xilinx Employee
Xilinx Employee
553 Views
Registered: ‎10-19-2015

Re: Ultrascal MIG Self Refresh mode

Hi @iamay88

PG150 v1.4 from April 4, 2018 states "The self-refresh feature always comes up with the save/restore feature and is not available
alone." on page 70. 

 

The IP will either re-calibrate or skip calibration by using the save&restore feature. If the contents of the DRAM need to be preserved, the save&restore feature is the only option forwards at this time. 

 

Save restore doesn't need to save the XSDB information off chip, it is possible to load the information into BRAMs on the FPGA if you have enough room. Does your intended use case power down the FPGA? 

 

There have been updates to the 2017.1 v2.2 DDR4 self-refresh exit cycle. Do you have the ability to test with 2017.3 v2.2 rev 2? 

The Xilinx DDR4 IP will not let you operate the DRAM normally after a self-refresh exit without a restore cycle. 

 

-M

 

 

 

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