07-01-2019 11:01 AM
I'm attempting to configure the MIG (Memory Interface Generator) from within a BlockDesign in Vivado 2018.3 to use a custom component (MT41K128M16XX-125) which is simply the MT41K64M16XX-125 with 'row' increased from 13 to 14.
I've not had any trouble creating this custom component in the past using Vivado 2015.4, but for some reason I just can't convince Vivado 2018.3 to do the same. Sometimes, it 'seems' to be successful, only to throw a Synth 8-549 port width mismatch error.
A couple of observations:
Here are the discrepancies that I've found:
Clearly there is a disconnect somewhere while MIG is Generating the core and files between the information that I provide and what is produced - plus it is inconsistent.
Can someone please provide some additional insight into the steps the MIG IP Generator takes to get from user input to generated files and offer a workaround or fix to help me get to the required 14 bits of DDR3 address.
07-08-2019 08:33 PM
Hello @taberski ,
This sounds like a known issue with the 7-Series MIG in 2018.3.
Can you take a look at AR#71898 and apply the Rev4 patch and let me know if that resolves if for you?
If you try this in 2018.2 it should work fine without any issues.
07-09-2019 02:14 PM
Thank you for this information. I installed the Patch as directed and created a new MIG core from scratch using Vivado 2018.3. I created a custom part (MT41K128M16XX-125) based on MT41K64M16XX-125 that has 14 rows versus 13.
Unfortunately - I still receive the same error
Though I trust I installed the patch as instructed (Method 1), it is not at all obvious that Vivado is aware that this patch exists. Is there any way to check that Vivado is using this patch? As the results are exaclty the same as before, it's as though the patch wasn't applied or simply does not address the problem I'm experiencing.
07-09-2019 04:02 PM
Hello @taberski ,
If the patch was installed correctly you'll see it called out as a suffix to your Vivado version. See in the screenshot below I'm running Vivado 2018.3 with the patch from AR71312 applied:
07-10-2019 10:02 AM
If that's the case, then I don't have the patch installed correctly!
Based on the instructions provided, I copied the contents of the zip file to my Xilinx Vivado install directory which in my case is at:
This directory contains:
I do not have a XILINX_PATH environment variable defined. I'm trying to understand if I need to add this variable (and how to add and make permanent) and whether is should be XILINX_PATH, XILINX_VIVADO, MYVIVADO or some other variable(s).
07-10-2019 10:50 AM
I ran the batch file:
I now have the environment variable:
but I still do not see AR71898 displayed after Vivado 2018.3.
I removed the MIG and added a new one (just in case the patch was applied but not displayed), but I get the same error.
07-10-2019 08:51 PM
Hello @taberski ,
I gave this a quick run on my Windows machine and here I just extracted the patch to my Vivado install directory inside a folder called patches:
After launching Vivado I can see that the patch is applied:
07-11-2019 11:41 AM
Based on your screenshot - I deleted the directory I had and copied the entire directory tree using the supplied directory name (i.e. AR71898_vivado_2018_3_preliminary_rev4). For some reason - that worked! I now have the patch (AR71898) displayed when I run Vivivado.
I will delete and re-Add the MIG and see if this fixes my issue and will post my findings.
07-11-2019 01:12 PM
OK - I got the patch installed which seems to solve my address mis-match problem, but now I have problems with placing the DGSes. In particular I get 48 instances of:
and 48 instances of:
Any idea at to why I'm getting these errors and thoughts on hope to fix?