UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor taberski
Visitor
201 Views
Registered: ‎03-02-2012

Unable to create a working Custom Component in MIG in Vivado 2018.3

I'm attempting to configure the MIG (Memory Interface Generator) from within a BlockDesign in Vivado 2018.3 to use a custom component (MT41K128M16XX-125) which is simply the MT41K64M16XX-125 with 'row' increased from 13 to 14.

I've not had any trouble creating this custom component in the past using Vivado 2015.4, but for some reason I just can't convince Vivado 2018.3 to do the same.  Sometimes, it 'seems' to be successful, only to throw a Synth 8-549 port width mismatch error.

A couple of observations:

  • The MIG in Vivado 2018.3 is not able to store the custom component.  Each time I attempt to re-customize the MIG, I need to recreate my custom component. Perhaps there is a directory that Vivado is unable to write to.
  • The MIG Block in the Block Design diagram shows the correct number of address lines for DDR3 (i.e. ddr3_addr[13:0].
  • The BlockDesign wrapper has the correct number of address bits (i.e. DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );)
  • The top-level BlockDesign file (BlockDesign.vhd in my case) also has the correct number of address bits (i.e. DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );)
  • Within this same file (BlockDesign.vhd), the module BlockDesign_mig_7series_0_0 also contains the correct number of address bits (i.e. ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );)
  • The assigned signal "mig_7series_0_DDR3_ADDR" is also correct in the assignment "DDR3_addr(13 downto 0) <= mig_7series_0_DDR3_ADDR(13 downto 0);" and "ddr3_addr(13 downto 0) => mig_7series_0_DDR3_ADDR(13 downto 0),"
  • The file "sources_1\bd\BlockDesign\ip\BlockDesign_mig_7series_0_0\mig_a.prj" lists my custom component (MT41K128M16XX-125) with a RowAddress of 14.

Here are the discrepancies that I've found:

  • The file "sources_1\bd\BlockDesign\ip\BlockDesign_mig_7series_0_0\BlockDesign_mig_7series_0_0\mig.prj" does NOT show my Custom Component and lists RowAddress as 13.
  • The Verilog file "\sources_1\bd\BlockDesign\ip\BlockDesign_mig_7series_0_0\BlockDesign_mig_7series_0_0\user_design\rtl\BlockDesign_mig_7series_0_0.v" uses 13 bits for ddr3_addr (i.e. output [12:0] ddr3_addr,).  Note: this is the file that is directly below the MIG  when the .xci entry in Sources -> Hierarchy is expanded.

Clearly there is a disconnect somewhere while MIG is Generating the core and files between the information that I provide and what is produced - plus it is inconsistent.

Can someone please provide some additional insight into the steps the MIG IP Generator takes to get from user input to generated files and offer a workaround or fix to help me get to the required 14 bits of DDR3 address.

Thank you,

Kevin Taberski

taberski@dyenco.com

(303) 776-4658

0 Kudos
8 Replies
Moderator
Moderator
151 Views
Registered: ‎11-28-2016

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

Hello @taberski ,

This sounds like a known issue with the 7-Series MIG in 2018.3.

Can you take a look at AR#71898 and apply the Rev4 patch and let me know if that resolves if for you?

https://www.xilinx.com/support/answers/71898.html

If you try this in 2018.2 it should work fine without any issues.

0 Kudos
Visitor taberski
Visitor
130 Views
Registered: ‎03-02-2012

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

Thank you for this information. I installed the Patch as directed and created a new MIG core from scratch using Vivado 2018.3.  I created a custom part (MT41K128M16XX-125) based on MT41K64M16XX-125 that has 14 rows versus 13.

Unfortunately - I still receive the same error

  • [Synth 8-549] port width mismatch for port 'ddr3_addr': port width = 13, actual width = 14 ...

Though I trust I installed the patch as instructed (Method 1), it is not at all obvious that Vivado is aware that this patch exists.  Is there any way to check that Vivado is using this patch? As the results are exaclty the same as before, it's as though the patch wasn't applied or simply does not address the problem I'm experiencing.

-Kevin

0 Kudos
Moderator
Moderator
121 Views
Registered: ‎11-28-2016

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

Hello @taberski ,

If the patch was installed correctly you'll see it called out as a suffix to your Vivado version.  See in the screenshot below I'm running Vivado 2018.3 with the patch from AR71312 applied:
vivado_with_patch.PNG

0 Kudos
Visitor taberski
Visitor
102 Views
Registered: ‎03-02-2012

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

If that's the case, then I don't have the patch installed correctly!

Based on the instructions provided, I copied the contents of the zip file to my Xilinx Vivado install directory which in my case is at:

C:\Xilinx\Vivado\2018.3\patches\AR71898

This directory contains:

  • data
  • lib
  • patch_readme

I do not have a XILINX_PATH environment variable defined. I'm trying to understand if I need to add this variable (and how to add and make permanent) and whether is should be XILINX_PATH, XILINX_VIVADO, MYVIVADO or some other variable(s).

Any thoughts?

Thank you,

-Kevin

0 Kudos
Visitor taberski
Visitor
97 Views
Registered: ‎03-02-2012

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

I ran the batch file:

C:\Xilinx\Vivado\2018.3\settings64.bat

I now have the environment variable:

XILINX_VIVADO=C:\Xilinx\Vivado\2018.3

but I still do not see AR71898 displayed after Vivado 2018.3.

I removed the MIG and added a new one (just in case the patch was applied but not displayed), but I get the same error.

Thank you,

-Kevin

0 Kudos
Moderator
Moderator
78 Views
Registered: ‎11-28-2016

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

Hello @taberski ,

I gave this a quick run on my Windows machine and here I just extracted the patch to my Vivado install directory inside a folder called patches:

windows_path.PNG

After launching Vivado I can see that the patch is applied:

patch_applied.PNG

0 Kudos
Visitor taberski
Visitor
62 Views
Registered: ‎03-02-2012

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

Based on your screenshot - I deleted the directory I had and copied the entire directory tree using the supplied directory name (i.e. AR71898_vivado_2018_3_preliminary_rev4).  For some reason - that worked!  I now have the patch (AR71898) displayed when I run Vivivado.

I will delete and re-Add the MIG and see if this fixes my issue and will post my findings.

Thank you,

-Kevin

0 Kudos
Visitor taberski
Visitor
53 Views
Registered: ‎03-02-2012

Re: Unable to create a working Custom Component in MIG in Vivado 2018.3

OK - I got the patch installed which seems to solve my address mis-match problem, but now I have problems with placing the DGSes. In particular I get 48 instances of:

  • [Place 30-69] Instance BlockDesign/BlockDesign_i/mig_7series_0/u_BlockDesign_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer

and 48 instances of:

  • [Place 30-68] Instance BlockDesign/BlockDesign_i/mig_7series_0/u_BlockDesign_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed

Any idea at to why I'm getting these errors and thoughts on hope to fix?

Thank you,

-Kevin

0 Kudos