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Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

Observer
Posts: 20
Registered: ‎02-20-2009

Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

I have a problem generating a memory controller for DDR3 part MT41K1G8SN-125. I want to clock it at 800Mhz to achieve 1600MB/s.

 

There is no MT41K1G8SN-125 in MIG option, then I used the part named MT41K512M8XX-125 and modified it with custom button (changed row from 10 to 11).

 

Controller is clocked at 200Mhz (sysclk) and I set the Design Clock Frequency at 1250ps to achieve 800Mhz.

 

At the end of MIG controller generation, frequency calculated are set to zero:

 

Controller Options :
   Memory                        : DDR3_SDRAM
   Interface                     : AXI
   Design Clock Frequency        : 1250 ps (  0.00 MHz)
   Phy to Controller Clock Ratio : 4:1
   Input Clock Period            : 0 ps
   CLKFBOUT_MULT (PLL)           : 0
   DIVCLK_DIVIDE (PLL)           : 0
   VCC_AUX IO                    : 2.0V
   Memory Type                   : Components
   Memory Part                   : MT41K1G8SN-125
   Equivalent Part(s)            : --
   Data Width                    : 8
   ECC                           : Disabled
   Data Mask                     : enabled
   ORDERING                      : Normal

Is it a MIG bug ? How can I solve this problem ?

 

Thanks,

 

 See above the all report generated :

 

 

Vivado Project Options:
   Target Device                   : xc7k160t-ffg676
   Speed Grade                     : -2
   HDL                             : verilog
   Synthesis Tool                  : VIVADO

If any of the above options are incorrect, please click on "Cancel", change the CORE Generator Project Options, and restart MIG.

MIG Output Options:
   Module Name                     : pea_pistis_mig_7series_0_0
   No of Controllers               : 2
   Selected Compatible Device(s)   : --

FPGA Options:
   System Clock Type               : Differential
   Reference Clock Type            : No Buffer
   Debug Port                      : 
   Internal Vref                   : disabled
   IO Power Reduction              : OFF
   XADC instantiation in MIG       : Enabled

Extended FPGA Options:
   DCI for DQ,DQS/DQS#,DM          : enabled
   Internal Termination (HR Banks) : 50 Ohms
    
/*******************************************************/
/*                  Controller 0                       */
/*******************************************************/
Controller Options :
   Memory                        : DDR3_SDRAM
   Interface                     : AXI
   Design Clock Frequency        : 1250 ps (  0.00 MHz)
   Phy to Controller Clock Ratio : 4:1
   Input Clock Period            : 0 ps
   CLKFBOUT_MULT (PLL)           : 0
   DIVCLK_DIVIDE (PLL)           : 0
   VCC_AUX IO                    : 2.0V
   Memory Type                   : Components
   Memory Part                   : MT41K1G8SN-125
   Equivalent Part(s)            : --
   Data Width                    : 8
   ECC                           : Disabled
   Data Mask                     : enabled
   ORDERING                      : Normal

AXI Parameters :
   Data Width                    : 32
   Arbitration Scheme            : RD_PRI_REG
   Narrow Burst Support          : 0
   ID Width                      : 4

Memory Options:
   Burst Length (MR0[1:0])          : 8 - Fixed
   Read Burst Type (MR0[3])         : Sequential
   CAS Latency (MR0[6:4])           : 11
   Output Drive Strength (MR1[5,1]) : RZQ/7
   Controller CS option             : Enable
   Rtt_NOM - ODT (MR1[9,6,2])       : RZQ/4
   Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
   Memory Address Mapping           : BANK_ROW_COLUMN


Bank Selections:

System_Clock: 
	SignalName: c0_sys_clk_p/n
		PadLocation: AC4/AC3(CC_P/N)  Bank: 34

System_Control: 
	SignalName: sys_rst
		PadLocation: No connect  Bank: Select Bank
	SignalName: init_calib_complete
		PadLocation: No connect  Bank: Select Bank
	SignalName: tg_compare_error
		PadLocation: No connect  Bank: Select Bank
/*******************************************************/ /* Controller 1 */ /*******************************************************/ Controller Options : Memory : DDR3_SDRAM Interface : AXI Design Clock Frequency : 1250 ps ( 0.00 MHz) Phy to Controller Clock Ratio : 4:1 Input Clock Period : 0 ps CLKFBOUT_MULT (PLL) : 0 DIVCLK_DIVIDE (PLL) : 0 VCC_AUX IO : 2.0V Memory Type : Components Memory Part : MT41K1GDSN-125 Equivalent Part(s) : -- Data Width : 8 ECC : Disabled Data Mask : enabled ORDERING : Normal AXI Parameters : Data Width : 32 Arbitration Scheme : RD_PRI_REG Narrow Burst Support : 0 ID Width : 4 Memory Options: Burst Length (MR0[1:0]) : 8 - Fixed Read Burst Type (MR0[3]) : Sequential CAS Latency (MR0[6:4]) : 11 Output Drive Strength (MR1[5,1]) : RZQ/7 Controller CS option : Enable Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/4 Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off Memory Address Mapping : BANK_ROW_COLUMN Bank Selections: System_Clock: SignalName: c1_sys_clk_p/n PadLocation: AA10/AB10(CC_P/N) Bank: 33

 

 

 

 

 

 

Moderator
Posts: 3,140
Registered: ‎02-06-2013

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

Hi

 

I didn't see this issue in 2016.4,can you try this?

 

In 2016.2 is this only the GUI or do you see the values being set wrongly in the generated hdl files too?

Regards,

Satish

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Observer
Posts: 20
Registered: ‎02-20-2009

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

> I didn't see this issue in 2016.4,can you try this?

 

I just upgraded my project to 2016.4 as you asked, but same problem.

 

> In 2016.2 is this only the GUI or do you see the values being set wrongly in the generated hdl files too?

 

I don't look into hdl files generated, but the final project doesn't work properly (Frequency of ddr3 is 200Mhz instead of 800Mhz).

Observer
Posts: 20
Registered: ‎02-20-2009

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

Ok I installed the new vivado version 2016.4  and upgraded my design.

To upgrade the mig component I deleted it and re-instatiated.

 

Now I have the right frequency in parenthesis :

Design Clock Frequency : 1250 ps ( 800.00 MHz)

 

But if I re-launch the MIG configurator by double-clicking on module in «options for controller 0 - DDR3 SDRAM» I have a wrong value at the bottom of window memory details:

 

 

Memory Details: -1.07374e+09Mb, x8, row:16, col:11, bank:3, data bits per strobe:8, with data mask, single rank, 1.35V, 15V

And the report display wrong frequency again :

 

Design Clock Frequency : 1250 ps ( 0.00 MHz)
Moderator
Posts: 3,140
Registered: ‎02-06-2013

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

 

Hi

 

Can you attach the mig.prj and xdc files

 

Also have you simulated or tested the example design generated in 2016.4 and still seeing issue's?

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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Observer
Posts: 20
Registered: ‎02-20-2009

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

I found the main problem: The Clock option was not displayed in Memory Options configuration menu as you can see on screenshoot above:

 

Pistis_ddr3_03.png

 

The only solution I found is to use another computer with windows 64bits and install vivado 2016.4 on it...

 

But the ddr3 size problem remain on windows in controller options :

 

ddr3_8Go_w64.png

 

Memory size should be 8Gb and not -1.07374e+09Mb.

 

I attached mig.prj and xdc file in message.

Moderator
Posts: 5,354
Registered: ‎09-20-2012

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

Hi @martoni

 

Can you please share the vivado 2016.4 IP XCI file too?

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Observer
Posts: 20
Registered: ‎02-20-2009

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

Moderator
Posts: 5,354
Registered: ‎09-20-2012

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

Hi @martoni

 

Thanks for sharing the XCI file.

 

I am able to reproduce this issue (incorrect density details shown in MIG IP) in vivado 2016.4 on windows-7 machine. However I dont see this issue in vivado 2017.1 (internal build) on windows-7. This issue will be fixed in our upcoming release 2017.1.

 

 

 

Capture.PNG

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Observer
Posts: 20
Registered: ‎02-20-2009

Re: Wrong Design Clock Frequency calculated in vivado 2016.2 for kintex7

I just installed the 2017.1 and I confirm that bug is fixed.