06-13-2018 04:00 AM
PG150 document mentions about the calibration done by DDR4 controller.
I would like to know whether the calibration detects the following,
1. Data line is short with another data line (either from same DQS group or different DQS group).
2. Data line is open.
3. Does it use address lines during calibration and if yes, does it detect shorts or opens for all the address lines.
06-13-2018 09:24 AM
The DDR4 controller calibration will be able to detect these conditions because the memory will be written and read with incorrect data.
Overall these conditions are pretty rare from my experience since it would have to be a very bad layout blunder or a large excursion in the assembly process for them to occur. Most people have issues meeting the DDR4 PCBA design guidelines in UG583 (link is in my signature) such as meeting the length matching guidelines while including the package pin flight delays. Some other common mistakes are trace impedance excursions, incorrect or missing termination resistors, and swapping the P/N or T/C components of a differential pair.
06-13-2018 09:16 PM
Thanks for your answer.
I wanted to use the DDR Calibration as reference for my assembled boards testing.
Thus if DDR calibration happened properly and the DDR controller module sets the calib_done pin, can I assume that all the data lines are proper from assembly point of view ( no short or open lines).
Then the only thing which we should test is the address lines. Please confirm.
06-14-2018 08:40 AM
Yes, that's correct. All the data lines (DQ, DQS, and DM pins if you're using them) will be tested but not all of the address lines.