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Xilinx UltraScale DDR4 Calibration Queries

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Participant
Posts: 56
Registered: ‎12-03-2013
Accepted Solution

Xilinx UltraScale DDR4 Calibration Queries

Hi All,

 

PG150 document mentions about the calibration done by DDR4 controller.

 

I would like to know whether the calibration detects the following,

 

1. Data line is short with another data line (either from same DQS group or different DQS group).

2. Data line is open. 

3. Does it use address lines during calibration and if yes, does it detect shorts or opens for all the address lines.

 

Regards

Ayusman


Accepted Solutions
Moderator
Posts: 293
Registered: ‎11-28-2016

Re: Xilinx UltraScale DDR4 Calibration Queries

Hello @ayusman100488,

 

Yes, that's correct.  All the data lines (DQ, DQS, and DM pins if you're using them) will be tested but not all of the address lines.

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Don’t forget to reply, kudo, and accept as solution.
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PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

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Moderator
Posts: 293
Registered: ‎11-28-2016

Re: Xilinx UltraScale DDR4 Calibration Queries

Hello @ayusman100488,

 

The DDR4 controller calibration will be able to detect these conditions because the memory will be written and read with incorrect data.

  1. In this case with the POD standard the shorted DQ lines will most likely not be at a valid voltage level for the expected data being written.
  2. If the data line is open then the expected data wouldn't be written or read
  3. The calibration does use the address lines but only a few of the lowest address bits so it's not a comprehensive test.  Here the Example Design using the Advanced Traffic Generator (non-AXI designs have this) then you will be able to test across the entire memory range and use all the address bits.  If there's an open or short then you also run in the possibility that the mode registers won't be programmed correctly and the DRAM wouldn't operate as expected.

 

Overall these conditions are pretty rare from my experience since it would have to be a very bad layout blunder or a large excursion in the assembly process for them to occur.  Most people have issues meeting the DDR4 PCBA design guidelines in UG583 (link is in my signature) such as meeting the length matching guidelines while including the package pin flight delays.  Some other common mistakes are trace impedance excursions, incorrect or missing termination resistors, and swapping the P/N or T/C components of a differential pair.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

Participant
Posts: 56
Registered: ‎12-03-2013

Re: Xilinx UltraScale DDR4 Calibration Queries

Hello @ryana,

 

Thanks for  your answer.

 

I wanted to use the DDR Calibration as reference for my assembled boards testing.

Thus if DDR calibration happened properly and the DDR controller module sets the calib_done pin, can I assume that all the data lines are proper from assembly point of view ( no short or open lines). 

 

Then the only thing which we should test is the address lines. Please confirm.

 

Regards

Ayusman

Moderator
Posts: 293
Registered: ‎11-28-2016

Re: Xilinx UltraScale DDR4 Calibration Queries

Hello @ayusman100488,

 

Yes, that's correct.  All the data lines (DQ, DQS, and DM pins if you're using them) will be tested but not all of the address lines.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

Participant
Posts: 56
Registered: ‎12-03-2013

Re: Xilinx UltraScale DDR4 Calibration Queries

Hi @ryana,

 

Thanks for the confirmation. I understand that not all address lines will be tested.

Can you please propose what will be the right way to test all address lines.

 

I was thinking if I write a walking 1 pattern to the axi slave address of the DDR IP and do a write and read back for each address bit, then all the physical address and control lines of the DDR shall be tested. Can you please confirm if my understanding is correct.

If not, can you please suggest a right way to do so.

 

Regards

Ayusman

Moderator
Posts: 293
Registered: ‎11-28-2016

Re: Xilinx UltraScale DDR4 Calibration Queries

hello @ayusman100488,

 

Yup, that would work.

When you get down to it the AXI address eventually maps to the memory address pins so a walking 1 would eventually toggle all the address bits on the interface.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

Participant
Posts: 56
Registered: ‎12-03-2013

Re: Xilinx UltraScale DDR4 Calibration Queries

Thanks @ryana.

 

This answers my question.

 

Regards

Ayusman