08-14-2019 05:48 AM
I am using Kintex US+ for driving DDR4 SDRAM
My logic consists of 3 parts. Axi4_Timing_Signal_generator + Axi Interconnect rtl + MIG for DDR4 SDRAM.
AXI4 Timing Signal Generator connected with axi Interconnect rtl's slave part.(by clock 245.76MHz)
And also, Axi Interconnect rtl's Master part connected with MIG Axi slave Interface(by ui_clk 300MHz)
I am trying to write & read counter decimal value(start with 0, 1, 2, 3, 4, 5, 6 ... 193 by clock 122.88MHz)
and also certify the read value if it is same or not with write value.
the access 32 bit address 0, 256, 512, 768, 1024. the data width is 128-bit(DDR4 DQ 16-bit, prefetch 8), Write & Read AXI Burst Length is 64.
I did simulation with test bench. the result of simulation is good.
But, when i drived the DDR4 SDRAM in real, Writing data was good(data, Address, timing all things). But data of read from DDR SDRAM with same address accessment was wrong.
the read data from DDR4 SDRAM 0,1,2,3235023580(?),4,5,6,7,238923898(?),8 .... 193.
I can see often trash value which i did not write in ILA.
the signal timing seems okay same as simulation value. But abnomal value has happened suddenly between normal value.
How can i solve this problem??
08-14-2019 08:58 AM
08-15-2019 09:30 PM
08-16-2019 02:17 AM
I can't read all of the low order bits of the garbage values you are struggling with. (The values don't fit in the trace.) The one I could read, 2056 when the value should've been 8, was curious simply because 2056 = 808h. This suggests that the memory data lines got corrupted either on read or write, since the low-order bits of the value are "correct" whereas the upper bits are not.
Are all of the errors such that the bottom 8-bits are still correct?