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209 Views
Registered: ‎09-07-2017

10G/25G High Speed Ethernet Subsystem

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Hi

from the pg210-25 ethernetsubsystem product guide , it's not clear if we are able to transmit a short packet < 64 bytes to the core.

Can anyone help me to see if there is a need to pad the packet size <64 bytes or the IP Will take care of the padding, and if we send a packet shorter than 64 bytes there will be abort of transmission from the core ? 

 

I appreciate your help

 

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Xilinx Employee
Xilinx Employee
188 Views
Registered: ‎09-05-2018

Re: 10G/25G High Speed Ethernet Subsystem

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Hey @bassem.sleiman ,

The core requires that all packets sent or reiceived are at least 64 bytes. Please see PG210 page 291:

Padding
The Pad field is not added by the 10/25G High Speed Ethernet IP. You must present a
packet that meets the minimum length to the IP core. When the IP core is configured to
calculate and add the FCS to the packet (ctl_tx_fcs_ins_enable = 1), the
minimum packet length is 60 bytes. If the FCS is calculated and added outside the IP
core (ctl_tx_fcs_ins_enable = 0), the minimum packet length is 64 bytes.

If you try to send or receive a small packet, the core should enable tuser and tlast indicating an error.

Nicholas Moellers

Xilinx Worldwide Technical Support
1 Reply
Xilinx Employee
Xilinx Employee
189 Views
Registered: ‎09-05-2018

Re: 10G/25G High Speed Ethernet Subsystem

Jump to solution

Hey @bassem.sleiman ,

The core requires that all packets sent or reiceived are at least 64 bytes. Please see PG210 page 291:

Padding
The Pad field is not added by the 10/25G High Speed Ethernet IP. You must present a
packet that meets the minimum length to the IP core. When the IP core is configured to
calculate and add the FCS to the packet (ctl_tx_fcs_ins_enable = 1), the
minimum packet length is 60 bytes. If the FCS is calculated and added outside the IP
core (ctl_tx_fcs_ins_enable = 0), the minimum packet length is 64 bytes.

If you try to send or receive a small packet, the core should enable tuser and tlast indicating an error.

Nicholas Moellers

Xilinx Worldwide Technical Support