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Visitor olliie
Visitor
133 Views
Registered: ‎03-08-2012

10G/25G High Speed Ethernet rx_clk_out_2 390.625

Hi,

I am using a 10/25G Etherent PCS/PMA core with 4 ports in vivado 2018.2 creating a block design

An odd thing appears to be happening with the rx_clk_out ports. port 0,1,3 are 312.5 MHz as you might expect. but port 2 is 390.625.

I cannot seem to set the CONFIG.FREQ_HZ value as it is locked. There is nothing special with port 2, so I guess this is  an error with vivado?

what can I do to resolve this?

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2 Replies
Xilinx Employee
Xilinx Employee
69 Views
Registered: ‎05-01-2013

回复: 10G/25G High Speed Ethernet rx_clk_out_2 390.625

These 4 ports should be the same.

You may compare all the input/output signals between the good port and the bad port, specially all the clock frequencies.

You can also generate IP core example design first and check if the example has the same issue in simulation.

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Visitor olliie
Visitor
60 Views
Registered: ‎03-08-2012

回复: 10G/25G High Speed Ethernet rx_clk_out_2 390.625

Hi,

Yes they all come out identical as 312.5 MHz.

 

pcs_pma_simulation.png

When I go through the component on the board however, there are a number of clocks with their frequency incorrectly defined.

pcs_pma_block.png

They are rxrecclkout_2(100MHz). tx_mii_clk_1(no freq). tx_mii_clk_2(390MHz). rx_clk_out_2(390MHz).

I have attached the tcl file to help someone recreate it. though it is pretty quick to create manually

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