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Visitor geerard
Visitor
5,380 Views
Registered: ‎07-25-2016

10GbE Local Fault detected - management clock dclk

I'm using the 10G Ethernet PCS/PMA core (ten_gig_eth_pcs_pma) from Xilinx in a Kintex-7 series FPGA to setup a communication channel between the KC705 development board and a PC using the SFP+ connector. When reading the status registers after reset, following registers are high: 48-231-250-256-268 (apart from the one who return a fixed value). The description of the corresponding bits is the following:

- Signal detected on receive
- Local Fault detected
- Receive Fault detected
- RX is synchronized
- 10GBASE-R receive is aligned

In addition, following bits are high:

- txuserrdy_out

- reset_counter_done_out

- resetdone_out

 

According to the pg068-10-gig-eth-pcs-pma.pdf document, Appx C: Debugging, the local fault has following most likely causes:

(A) The transceiver has not locked or the receiver is being reset.
(B) The block lock state machine has not completed.
(C) The BER monitor state machine indicates a high BER.
(D) The elastic buffer has over/underflowed.

Cause (A) is unlikely, since the corresponding register (256,10GBASE-R PCS RX Locked) is high and the resetdone_out bit is high

Cause (B) is unlikely, since the corresponding register (287,Latched Low RX Block Lock) is low

Cause (C) is unlikely, since the corresponding register (286,Latched High RX high BER) is low

 

(1) How to check/clear the elastic buffer? At the XGMII interface, I supply idle frames when not transmitting. When transmitting, I'm creating a frame in the Ethernet standard. I'm currently not using the Rx side. At the PC, I'm capturing the packets using Wireshark, and the PC only transmits a 307-byte UDP packet every 15 sec.

 

(2) Another question regarding the management clock dclk: I cannot find the allowed frequencies for this clock. Which frequency should I take?

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3 Replies
Moderator
Moderator
5,054 Views
Registered: ‎02-16-2010

Re: 10GbE Local Fault detected - management clock dclk

For block lock failure, please check the status vector also to confirm.
Also, check the design in SFP+ loopback.
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Adventurer
Adventurer
2,506 Views
Registered: ‎02-19-2016

Re: 10GbE Local Fault detected - management clock dclk

I'm experiencing this same exact issue in simulation. I'm using my txp/txn ports as inputs to the rxp/rxn.  Additionally, my pcspma_status[7:0] vector is a 8'b1, which corresponds to PCS Block Lock.

 

As anyone solved this?

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Xilinx Employee
Xilinx Employee
2,493 Views
Registered: ‎04-16-2008

Re: 10GbE Local Fault detected - management clock dclk

If you have not already, I'd suggest running the example simulation and comparing inputs and simulation run time to your simulation.

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