08-04-2016 05:53 AM
I'm using the 10G Ethernet PCS/PMA core (ten_gig_eth_pcs_pma) from Xilinx in a Kintex-7 series FPGA to setup a communication channel between the KC705 development board and a PC using the SFP+ connector. When reading the status registers after reset, following registers are high: 48-231-250-256-268 (apart from the one who return a fixed value). The description of the corresponding bits is the following:
- Signal detected on receive
- Local Fault detected
- Receive Fault detected
- RX is synchronized
- 10GBASE-R receive is aligned
In addition, following bits are high:
According to the pg068-10-gig-eth-pcs-pma.pdf document, Appx C: Debugging, the local fault has following most likely causes:
(A) The transceiver has not locked or the receiver is being reset.
(B) The block lock state machine has not completed.
(C) The BER monitor state machine indicates a high BER.
(D) The elastic buffer has over/underflowed.
Cause (A) is unlikely, since the corresponding register (256,10GBASE-R PCS RX Locked) is high and the resetdone_out bit is high
Cause (B) is unlikely, since the corresponding register (287,Latched Low RX Block Lock) is low
Cause (C) is unlikely, since the corresponding register (286,Latched High RX high BER) is low
(1) How to check/clear the elastic buffer? At the XGMII interface, I supply idle frames when not transmitting. When transmitting, I'm creating a frame in the Ethernet standard. I'm currently not using the Rx side. At the PC, I'm capturing the packets using Wireshark, and the PC only transmits a 307-byte UDP packet every 15 sec.
(2) Another question regarding the management clock dclk: I cannot find the allowed frequencies for this clock. Which frequency should I take?
08-12-2016 09:47 AM
05-01-2017 08:34 AM
I'm experiencing this same exact issue in simulation. I'm using my txp/txn ports as inputs to the rxp/rxn. Additionally, my pcspma_status[7:0] vector is a 8'b1, which corresponds to PCS Block Lock.
As anyone solved this?
05-01-2017 12:35 PM
If you have not already, I'd suggest running the example simulation and comparing inputs and simulation run time to your simulation.