01-18-2018 03:31 PM
In my design I have implemented the 1G/2.5G PCS/PMA or SGMII core with the following configuration:
I am trying to test the design on the Avnet MiniITX development board and I am having no luck with establishing a link with an external device. Looking at the ILA traces I notice that the resetdone signal never gets asserted. I have traced my system reset as well as mgt_tx_reset and mgt_rx_reset and all of them behave accordingly. Also auto negotiation is enabled both side (dev board and the server). I am running out of ideas what could be preventing the resetdone from going high. Any help is much appreciated.
01-21-2018 08:39 PM
In 7 Series the startup FSM checks for data valid which is asserted by core after receiving valid sync words from the link partner to finish the reset sequence.
Can you add the transceiver rx reset fsm to check at which state the sequence is getting struck along with the data valid,rxdata,txdata,notintable,disperr and status_vector signals in the corename_block.v/vhd module to ILA and share the captures for review.
Also check if transceiver near end loopback is able to get the link up.
01-24-2018 10:29 AM
Thank you for your reply. Before we go further I would like to clarify some concepts. What I am trying to achieve is to establish at Ethernet link over copper using the optical-to-copper adapter in an SFP cage. My understanding is that 1000Base-X is for fiber and 1000Base-T is for twisted pair cabling. In the core I have the option to chose 1000Base-X, SGMII, or both. So far I had the core generated with the 1000Base-X option. What is the correct option to allow me achieve my goal of fiber to copper (1 GigE) conversion?
01-24-2018 01:35 PM
Hi, the interface you need to configure the PCS/PMA core for will depend on your copper SFP. Copper SFPs have a PHY internal to the SFP that converts from 8b10b encoded 1000BASE-X or SGMII to BASET used over the RJ45 port. Some support 1000BASE-X with or without Auto-Negotiation and some support tri-speed SGMII by default. Often the PHY inside the SFP can be configured for desired interface over I2C.
I'd recommend checking the SFP datasheet if you have one. Otherwise you could try generating PCS/PMA core with both SGMII and 1000BASE-X and try switching between two and turning on/off Auto-Negotiation.
The checks Satish suggested earlier are also good to confirm there isn't any issue with clock, reset or something else in the FPGA design.
01-25-2018 12:59 PM
The optical to copper module that I am using is the Finisar FCLF-8521-3 which is 1000BASE-X compliant with PHY configured to perform auto-negotiation with the host system. In my application the host (custom board) is always in transmit mode to an external device (server). Therefore I have set the configuration vector of the 1G/2.5G core to 5'b00001 to set is as transmit only. For my application I need to have AN enabled because I do not have any control on the server side. Still I am unable to establish a link. I have noticed that the rxresetdone never gets asserted. Will that signal be asserted even if I am TX only?
01-25-2018 02:16 PM
Finisar FCLF-8521-3 is configured for 1000BASE-X with AN on link with FPGA by default. AN requires bi-directional connection to complete as it requires exchange of information. You will not be able to get link up if one side of 1000BASE-X link has AN enabled and one side does not have AN enabled. To talk to Finisar FCLF-8521-3 in default configuration you will want the PCS/PMA core configured for 1000BASE-X with configuration vector 4:0=10000. Unidirectional enable can only be used if both sides of 1000BASE-X link have AN disabled. I2C can be used to disable AN on Finisar side of 1000BASEX link, but not sure if that is necessary? Have you tried with configuration vector 4:0=10000.
01-26-2018 12:05 PM
I do have configuration vector set as 5'b10000. What should the an_adv_config_vector be set to? Also, just to recap AN will not work if in the link one side is TX only, which is the case for me.
01-29-2018 09:10 AM
If you plan to only transmit packets, but still have RX and TX lines connected between the Xilinx FPGA and the PHY that is inside the Finisar copper SFP then 1000BASE-X AN should still be able to complete. Do you have link up on the BASET interface between the copper SFP and your link partner? There will be initial AN that takes place between PHY in the SFP and link partner over BASET interface. Does link partner support 1G?
It would still be helpful to do ILA capture that Satish suggested earlier.
02-01-2018 08:13 PM
There is AN between the 1000Base-T (copper) and the client but the 1000Base-X AN never completes. The resetdone of the core also never asserts. I have attached the ILA capture of a run with AN off and I will attach one with the AN enabled in my next post. On the client side it shows that the link is up but there is no data transfer.
02-05-2018 09:12 AM
That is good news that the client side indicates that the 1000BASE-T AN is completing and that link between far-end client and SFP is up. That means focus should continue to be on 1000BASE-X interface between the SFP and Xilinx.
The ILA captures you have shared show very frequent rx disparity errors and not in table errors for the RX data coming out of the GT. Synchronization is not able to complete to even start AN.
Does near-end loopback work?
Can you confirm the reference clock frequency for the GT matches the reference clock frequency set for the core?
02-08-2018 11:34 AM
I was able to establish a link. There was an issue with the gt_refclk frequency and once that was resolved I have a link. I am in the process of checking the validity of the data that I collect. Thank you for the help.
07-13-2018 11:17 PM
07-24-2018 06:25 AM