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Visitor edi-301090
Visitor
3,327 Views
Registered: ‎08-25-2017

AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi,

I’m using the AXI Ethernet Subsystem v7.1 in Vivado 2017.2. My great dream is to stream IPv4/UDP-Ethernet-Packets with the integrated function “full Checksum Offload” to calculate the IPv4- and UDP-checksum. Additionally the FCS (Frame Check Sequence) of the Ethernet-Packed should be calculated by the Ethernet-Subsystem-IP (high priority).

So, there are several conditions described in the datasheet of the Ethernet-Subsystem-IP. In my opinion all this conditions are fulfilled. But it doesn’t work as expected. But step by step:

 

My register entries are:

0x000: 0x0000 0000

0x404: 0x9000 ffff (reset, receive enable)

0x408: 0x9000 0000 (reset, transmit enable)

0x40c: 0x6000 0000

0x500: 0x0000 005d (MDIO enable and clock divide)

0x504: 0x0301 4800 (PHY-address, write-access, Initiate MDIO transfer)

0x700: 0x0135 0a00 (MAC-address word 0)

0x704: 0x0000 0302 (MAC-address word 1)

0x750: 0xffff ffff (mask value)

 

My Ethernet-Frame looks exactly like the frame described on page 15 in datasheet:

frame_udp_ipv4

My Configuration Words (TXC) are (described on page 105):
Word 0: 0xa000 0000 (Normal Transmit Frame)

Word 1: 0x0000 0002 (FULL Checksum Offload)

Word 2: 0x000E 0028 (Starting Point for Checksum Calc. 14 Byte = 0xE; Offset for Insert: 0x28)

Word 3: 0x0000 F0F0 (necessary in FULL Checksum Offload?)

Word 4: 0x0000 0000

Word 5: 0x0000 0000

 

Out of several test cases I documented two interesting cases for you:

 

First Case:

Use the TXC-signals exactly as shown in datasheet (page 103):

page103

(The signals axi_str_txd_tstrb(3:0) and axi_str_txc_tstrb(3:0) are not available in the IP (red marked in graphic). Why?)

 

My Waveform-result (ILA):

ethernet_subsystem_checksum_failed

 

So: The TXC_tready signal goes down before the TXC_tlast signal has detected (although I didn’t send all configuration-words yet). I just sent two config-words. That’s why the TXD_tready never go high. So I never can send my TXD_tdata. Why goes txc_tready down?

 

Second Case:

My Waveform-result (ILA):

ethernet_subsystem_checksum_failed_2.PNG

A few words about this waveform: In this test case I tried to send the configuration words (TXC_tdata) before my TXD_tvalid goes hi. Only in the case (for tests) that all configuration-words are 0x00000000 (TXC_tdata), the Ethernet Subsystem sets TXD_tready high to give me the chance to send my data. In this special case it is possible to send my Ethernet-packet to another device (detected in wireshark for example).

BUT: The detected Ethernet-packet in wireshark (shown in picture) is exactly the same packet, which I am sending by using the Ethernet Subsystem. The problem is: neither UDP, nor IPv4, nor FCS-Checksums is calculated by the Ethernet Subsystem. The checksums you can see in this graphic (44 55 (IPv4), 66 77 (UDP) and 99 99 88 88 (FCS)) are manual inserted at the beginning. I hoped, this would be replaced… of course, too much hoping!

 

wireshark

Picture: Wireshark on Destination.

 

I already tried the “partial Checksum Offload”. This case also didn’t work.

 

Well, do you have any idea, what error am I doing?

 

My other open questions / ideas for solution are:

  1. Where are the signals axi_str_txd_tstrb(3:0) and axi_str_txc_tstrb(3:0)? They are not part of the AXI-Streaming Interface in the Ethernet Subsystem. So it is not possible for me to write them.
  2. Is it necessary to enable 1588 in Ethernet-Subsystem IP? This mode is not available for me.
  3. Will the UDP-Checksum be replaced or inserted by the IP?
  4. Will the IPv4-Checksum be replaced or inserted by the IP?
  5. Will the FCS be replaced or inserted by the IP?
  6. Configuration words: little endian or big endian?
  7. Configuration words: Write Config-words 0 to 6 or 6 to 0?
  8. Are all register-entries correct?
  9. To conditions of the Ethernet-frame: It says “IP Options are not supported”. So, do I have to leave this part away, right? But why is PADDING red marked?

 

Maybe you need this information:

I don’t use DMA-IP: I’m using Streaming Fifo. I wrote a separate logic to write the Control-Words (streaming interface TXC). I’m not using a processor like Microblaze. The configuration of the Ethernet-Subsystem is made over a Linux-Shell-Skript->Userspace-Programm->PCIe-Driver and the DMA/Bridge-Subsystem-IP… But to explain all this things in detail would go beyond the scope.

Because of my FPGA-Board I configured the Ethernet-Subsystem with RGMII.

If you need more details, please let me know.

 

Many thanks in advance for your help :-)

 

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Xilinx Employee
Xilinx Employee
5,166 Views
Registered: ‎02-06-2013

Re: AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi Stefan,

 

How and where are you observing the FCS field(wireshark,ILa or RX axi stream)?

 

 

Regards,

Satish

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Visitor edi-301090
Visitor
3,063 Views
Registered: ‎08-25-2017

Re: AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi Everyone,

 

I solved a few problems and would like to keep you up to date:

Now the Full Checksum Offload works for me. The UDP and IPv4-Checksum is calculated correct by the Ethernet Subsystem.

The FCS-calculation is still missing.

 

Error solution for "Full Checksum Offload":

Do it NOT like shown in Datasheet (Figure 3-2: Page 103): The control-words have to be sent over AXI-Stream Control-Interface immediately. The TXD-tvalid signal must not be set yet. I solved the problem by sending the control-words directly after reset or when a falling edge of TXD-tvalid is detected.

 

Now I can answer a few of my questions:

1. The signals axi_str_txd_tstrb and axi_str_txc_tstrb are still not there, but not necessary.

2. Mode 1588 is not necessary for Full Checksum Offload (UDP and IPv4). But what is about FCS?

3. The Ethernet Subsystem replace (not insert) the UDP-Checksum in Ethernet-Frame.

4. The Ethernet Subsystem replace (not insert) the IPv4-Checksum in Ethernet-Frame.

7. Write Config-words 0 to 6. In Full-Checksum-Offload-Mode the Config-words 0 to 1 are enough.

9. The region "IP Options" must not be part of the Ethernet-frame. Ignore the PADDING written in red.

 

Now the only problem is the missing FCS calculation/insertion.

Once again I have 3 interesting cases:

 

First Case:

Set bit 29 in register 0x408 (TEMAC Transmit Config) to 1:

FCS field is provided with transmit frame data:

I have sent a simple ethernet-frame (without UDP and IPv4) like:

-Destination Address

-Source address

-Length

-Payload

-FCS (correct!).

 

The Ethernet Subsystem has sent my Ethernet frame but without my calculated FCS. So, the IP removed the FCS from the Ethernet frame.

 

Second Case:

Same as in Case 1, but with wrong FCS:

The Ethernet Subsystem rejected the complete frame. Nothing has been sent.

 

Third Case:

Unset bit 29 in register 0x408 (TEMAC Transmit Config) to 0:

I have sent a ethernet-frame (no matter which type) without FCS:

The Ethernet Subsystem has sent the Ethernet frame without FCS.

 

In all cases the checksum is not inserted by the Ethernet Subsystem. Is there a special bit I have overlooked?

Do you have an idea how to solve the problem?

I would be very thankful.

 

Kind Regards,

Stefan

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Xilinx Employee
Xilinx Employee
3,056 Views
Registered: ‎02-06-2013

Re: AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi

 

1588 is not needed for FCS insertion.

 

In order for the transmit checksum to be calculated correctly, the transmit Ethernet FCS must not be provided as part of the transmit data and the transmit FCS calculation and insertion must be enabled in the AXI Ethernet Subsystem.

 

Regards,

Satish

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Visitor edi-301090
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Registered: ‎08-25-2017

Re: AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi Satish,

 

thank you very much for your reply.

In my opinion this conditions are fulfilled in "case 3":

Condition 1: Register 0x408 Bit 29: Reset to 0.

Condition 2: My Ethernetframe do not provide FCS

 

But the AXI Ethernet Subsystem doesn't insert the FCS. Is something else to be observed?

 

Regards,

Stefan

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Re: AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi Stefan,

 

How and where are you observing the FCS field(wireshark,ILa or RX axi stream)?

 

 

Regards,

Satish

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Visitor edi-301090
Visitor
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Registered: ‎08-25-2017

Re: AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi Satish,

 

I observed the transfer on several ways.

My Hardware has 2 Phy's. The first is my source, the second my destination.

On a third ethernet interface (of my linux-pc) I have the option to observe the transfer via wireshark.

wireshark.png

The "0x99 99 88 88" is part of my payload (not the FCS), which is considered in udp and ipv4-lenth-fields.

 

I also checked the RX-axi stream on ILA (over the second Phy: My Destination).

ILA.PNG

On both ways I detected the same result: No FCS.

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Visitor edi-301090
Visitor
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Registered: ‎08-25-2017

Re: AXI 1G/2.5G Ethernet Subsytem FCS and Full Checksum Offload

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Hi Satish,

 

thank you for the question :-D

Before your reply I just checked the Ethernet-Frame on wireshark.

Now, after a reload of the bitstream I can see the FCS in ILA on RX-Stream.

The FCS is not shown in wireshark.

 

I would never have had the idea that wireshark does not display the FCS in this case.

 

Thank you very much!

 

 

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