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Visitor davee
Visitor
1,896 Views
Registered: ‎06-07-2017

Aurora 64B/66B RTL Implementation

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Hi.

I am wondering if anyone has synthesised and implemented an Aurora core for
an Ultrascale device using the RTL code instead of .dcp files. (Vivado 2016.2)?

I have tried to do this but I am unable to synthesise the fifo_generator_v13_1_1 component
that is used within the Aurora IP. This is because it uses encrypted IP and I get the
following error:

ERROR:[Synth 8-5809] Error generated from encrypted envelope.

 

This is when I use the encrypted files provided for synthesis:
fifo_generator_v13_1_vhsyn_rfs.vhd
fifo_generator_v13_1.vhd


If I do not provide these files, then I can get a synthesised design that has
blackboxes for fifo_generator_v13_1_1 components, but these then cause the
implementation to fail?

 

I need to know how I can either synthesise fifo_generator_v13_1_1 or
how do I replace the blackbox during implementation.

(I should mention that I can successfully synthesise/implement the Aurora
core using .dcp files, however I want to be able to modify the RTL design, hence the
need to be able to build from RTL.)

 

Thanks.

 

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Visitor davee
Visitor
2,925 Views
Registered: ‎06-07-2017

Re: Aurora 64B/66B RTL Implementation

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Thanks for your reply zheny.

 

I have now solved the problem by generating .dcp files at the level in the code hierarchy, for the modules

that incorporate  the fifo_generator_v13_1_1 module. In the Ultrascale Aurora core, fifo_generator_v13_1_1 gets

used in modules user_defined_name_fifo_gen_master and user_defined_name_fifo_gen_slave. In my naming convention

the modules are aurora_64b66b_12lane_fifo_gen_master and aurora_64b66b_12lane_fifo_gen_slave. I have generated

.dcp modules for these modules; aurora_64b66b_12lane_fifo_gen_master.dcp and aurora_64b66b_12lane_fifo_gen_slave.dcp.

 

This now allows me to synthesise the individual RTL files used in my design, and use the above .dcp files during implementation.

I now do not need to use the top-level Aurora aurora_64b66b_12lane.dcp file to build my design, and now have the ability to 

edit/synthesise the RTL if required.

 

If you have no need to edit the RTL code, and can use the Aurora core generated by IP Catalog, then I would recommend that the top-level .dcp file provided by the tools is used.

 

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Xilinx Employee
Xilinx Employee
1,761 Views
Registered: ‎03-07-2012

Re: Aurora 64B/66B RTL Implementation

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Hi 

 

Could you try to set the file to the following library?

 

1 blk_mem_gen_v8_3_vhsyn_rfs.vhd        blk_mem_gen_v8_3_3
2 blk_mem_gen_v8_3.vhd                        blk_mem_gen_v8_3_3
3 fifo_generator_v13_1_vhsyn_rfs.vhd     fifo_generator_v13_1_1
4 fifo_generator_v13_1.vhd                      fifo_generator_v13_1_1

 

 

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Visitor davee
Visitor
2,926 Views
Registered: ‎06-07-2017

Re: Aurora 64B/66B RTL Implementation

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Thanks for your reply zheny.

 

I have now solved the problem by generating .dcp files at the level in the code hierarchy, for the modules

that incorporate  the fifo_generator_v13_1_1 module. In the Ultrascale Aurora core, fifo_generator_v13_1_1 gets

used in modules user_defined_name_fifo_gen_master and user_defined_name_fifo_gen_slave. In my naming convention

the modules are aurora_64b66b_12lane_fifo_gen_master and aurora_64b66b_12lane_fifo_gen_slave. I have generated

.dcp modules for these modules; aurora_64b66b_12lane_fifo_gen_master.dcp and aurora_64b66b_12lane_fifo_gen_slave.dcp.

 

This now allows me to synthesise the individual RTL files used in my design, and use the above .dcp files during implementation.

I now do not need to use the top-level Aurora aurora_64b66b_12lane.dcp file to build my design, and now have the ability to 

edit/synthesise the RTL if required.

 

If you have no need to edit the RTL code, and can use the Aurora core generated by IP Catalog, then I would recommend that the top-level .dcp file provided by the tools is used.

 

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