06-15-2011 07:58 AM
I have a design partitioned over 2 FPGAs. I am trying to determine the benefits of selecting GTX links vs. LVDS to transfer the data between FPGAs.
Target Device : xc6vlx550t
Target Package : ff1759
Target Speed : -2
1. GTX interface: The GTX transceiver is configured at 106.25 MHz with 20 bits input. This means the bits are transmitted at bit-rate = 20*106.25 MHz = 2.125 Gbps.
# of bits to be transferred = 1728
Latency of this interface = 1/(80% of bit-rate * (20/16)*(# of bits transferred/16)) = 1/(2.295+e11) = 4.35+e-12 seconds
2. LVDS+Aurora: The Aurora interface is configured at 600MHz (6 Gbps) with lane width as 2 bytes.
Latency of this interface = 1/(80% of clock rate * (# of bits transferred/16)) = 1/(5.184+e10) = 19.29+e-12 seconds
Is this calculation correct? My assumption for the LVDS calculation is that Aurora does not up-sample the clock frequency by 20 for transmitting data.
Thanks in advance for all the feedback.
06-15-2011 11:09 AM
The GT has registers, and fifo's. These add latency. Read the user's guides, and look up the latencies. The Aurora core also has registers, fifo's. That is more latency.
It will be very hard to beat the LVDS wide parallel path for controllable latency. The latency pf the wide parallel bus is a clock to send it, and a clock to receive it. If the clock is 2ns (500 MHz) that in 4ns.
06-16-2011 03:03 AM
09-01-2011 05:27 PM
CAn you give us the minimum latency to transfer 64 bit with Aurora, Rapid IO and low level GTX.
Our simulation gives 500 nanos, which is certainly excessive and due to a bad setting. But I would like to know typical latency figures that we should expect