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Observer anjali_apex
Observer
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Registered: ‎05-01-2019

Experiment with aurora8b10 example design

I am trying to setup and transfer data between two FPGA( ML605).

So, I took that example from here https://www.xilinx.com/support/documentation/application_notes/xapp1193-aurora-8b10b-on-kc705.pdf ( this was made in vivado design suite with some other board) , but I am using ML605 and ISE design suite.

I generated the aurora8b10_example design (top_module) along with other module defines in it. I was able to synthezie and and generate the programming file.

But, Now I do not know what data is it sending and how are those thinngs happening for single lane.

and in the ucf file that it has generated does not have all input output that it has defined in the top module.

kindly help.

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Xilinx Employee
Xilinx Employee
62 Views
Registered: ‎05-01-2013

回复: Experiment with aurora8b10 example design

Here's Aurora 8B10B product guide.

https://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b/v11_1/pg046-aurora-8b10b.pdf

 

You can add ILA into your design to check the internal signals.

You can also try Near end loopbac first.