07-09-2015 05:28 PM
VC707 - transceivers wizard 3.5 ...
How do I with GTX transceiver wizard set CPLLREFCLK="101" so I can select my gt0_gtsouthrefclk0_in (which I'm in QUAD 113 so this is from QUAD114 correct)?
I currently have to open ..._multi_gt.vhd and the _funcsim.vhd/.v files and edit the:
SIM_CPLLREFCLK_SEL => "101",
cpllrefclksel_in => "101",
from the default "001"
The attached is my current .xci. --
I'm not sure about wizard page Line Rate,RefClk the "Transceiver Selection" I have my GTX X1Y2 from QUAD0 o ngui =QUAD113 for real set to get clk from QUAD1 per gui=QUAD114 for real REFCLK0_Q1 to my CPLL ... not sure what this does but closest thing to selecting the southrefclk0 I guess...?
I also include shared logic in example design since I think I don't want to step on my prior pcs_pma core that used include shared logic but still uses same QUAD113 - ch1 for phy.
I tried to find in .xci or report_property something to set the CPLL sel but don't see it..
currently I will set my .xci to global and delete my .dcp which will then just build from source right..
PS- when I change funcsim CPLLSEL signals it doesn't seem to simulate for them, just the "001"...?
07-20-2015 06:14 PM
07-13-2015 04:20 AM
07-13-2015 07:05 AM
Thanks, I've been looking at those diagrams for some time and just don't understand clearly. May you please point me the right direction for my application:
VC707 board, using QUAD113 the SGMII on GTXE_CHANNEL_X1Y! is already working using it's MGTREFCLK0 SGMII_CLK and now I want to get the GTXE2_CHANNEL_X1Y2 SFP+ transceiver in the same QUAD113 working using the Si5324 MGTREFCLK0 from QUAD114 as it's CPLL input.
I can't get CPLL lock. Since this Si5324 clk is from QUAD114 MGTREFCLK0 above I believed I should tie my design Si5324 clk input pin signals through an IBUFDS_GTE2 to the GTSOUTHREFCLK0 pin of my gtwizard GTXE2_CHANNEL for my SFP+ transciever. However in the design view it appears the Si5324 clk pin into QUAD 114 is mapping to GTSOUTHREFCLK1 in the diagram so I tried that as well. I've also tried to just tie it to GTREFCLK0 and/or 1, change to appropriate CPLLREFCLKSEL, and also to tie it to all the advanced clks...
Where shoudl I tie the Si5324 clk input signal -- what should my CPLLREFCLKSEL be set to.
If I understand your response it sounds like since I'm never changing clks to the SFP transceiver and only tieing one, I just leave CPLLREFCLKSEL = '001' and tie it to the GTREFCLK0?
07-14-2015 02:52 AM
07-15-2015 12:27 PM
I did as you said see instantiation but the picture from tools gui shows it didn't tie it to gtrefclk0 - even though i did in my vhdl the signal for somereason appears to go to gt0_gtsouthrefclk1_in ?!
Any ideas why?
I changed the CPLLREFCLKSEL = '001' as you said as well.
You can see I only hooked up gt0_gtrefclk0_in => clk_stm1_pregtx, and tied the north/south and refclk1 to gnd '1' -- is that correct?
I still don't get any cpll lock in hardware? (trying to get simulation to work which did before fine using funcsim, but no trying to use src files and IS_.*_INVERTED generics cause error out.. which I had to comment out in the funcsim...)
07-15-2015 01:59 PM
The only way I get the sim to work is using the verilog funcsim file and comment out the IS_.*_INVERTED lines. Wanted to sim from the source code but get's errors due to the IS.*INVERTED generics .. maybe my unisim library out of date?
Anyways - I get cpll lock and resets complete in simulation --- but in hardware I can never get cpll lock -- its like it doesn't even see the clk ... which is why i'm still curious if southrefclk1 as seen in design view should be used instead of your recommended refclk0? Then would the cpllrefclksel values need to be changed....
will continue to try different things...
07-15-2015 03:57 PM
- also any time I tie my clk_stm1 (the Si5324 clk) to the gt0_gtrefclk0_in as you recommended I get the below during DRC check? I can override and build the .bit file but I think this is telling me it never connected this clk to this pin.. while it does connect it to the GTSOUTHREFCLK0 or 1 pin fine if I connect it to those as well, and they don't give a similar error...?
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 8 threads
ERROR: [Drc 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem net(s) are top/main_wrapper_0/rlp_transition_0/gt0_gtrefclk0_in.
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 76 Warnings, 246 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:33 ; elapsed = 00:00:18 . Memory (MB): peak = 5227.184 ; gain = 162.648
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
07-20-2015 11:16 AM
07-20-2015 06:14 PM