UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
7,089 Views
Registered: ‎05-12-2014

Implementing the 7 Series FPGAs Transceivers Wizard example design in 2014.1

Jump to solution

Hello,

 

I am attempting to implement the 7 Series FPGAs Transceivers Wizard v3.2 example design in Vivado 2014.1 so that I can try running it in hardware using an Artix-7 AC701 Evaluation Kit. According to the "Implementing Using the Vivado Design Tools" section of chapter 6 in PG168:

 

 

"After wrapper generation is complete, the results can be tested in hardware. The provided example design incorporates the wrapper and additional blocks allowing the wrapper to be driven and monitored in hardware. The generated output also includes several scripts to assist in running the software.

 

From the command prompt, navigate to the project directory and type the following:

 

For Windows:

    > cd xaui_wrapper\implement

    > implement.bat

 

Note: Substitute Component Name string for xaui_wrapper.

 

These commands execute a script that synthesizes, builds, maps, places, and routes the example design and produces a bitmap file. The resulting files are placed in the implement/results directory."

 

 

Unfortunately, I cannot find implement.bat or any other generated batch file or TCL script that looks like it would do the job. Am I missing something here? Has this functionality been removed from the example design?

 

Thanks in advance for your help!

 

Best regards,

Dave

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
12,687 Views
Registered: ‎07-23-2012

Re: Implementing the 7 Series FPGAs Transceivers Wizard example design in 2014.1

Jump to solution

Hi Dave,

The implement.bat file is not generated in vivado.

 

You can use the below tcl command to generate the .tcl file in the TCL console of the example design project-

 

launch_runs synth_1 impl_1 -scripts_only

 

This will generate two tcl files- one for synthesis (in <core_name>_example.runs\synth_1) and one for implementation (in in <core_name>_example.runs\impl_1) 

Regards,
Krishna

-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
12,688 Views
Registered: ‎07-23-2012

Re: Implementing the 7 Series FPGAs Transceivers Wizard example design in 2014.1

Jump to solution

Hi Dave,

The implement.bat file is not generated in vivado.

 

You can use the below tcl command to generate the .tcl file in the TCL console of the example design project-

 

launch_runs synth_1 impl_1 -scripts_only

 

This will generate two tcl files- one for synthesis (in <core_name>_example.runs\synth_1) and one for implementation (in in <core_name>_example.runs\impl_1) 

Regards,
Krishna

-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
0 Kudos