Hello Xilinx Community,
this is my first post and I hope i got into the right forum. Thank you all in advance for your help.
At my company an ADC design is pending that must use a JESD204b Subclass 0 interface. To interface with the ADC a Xilinx XC7K70T is proposed. The line rates are somewhat low between 300 Mbps and 600 Mbps depending on the final configuration.
I have now read in the JESD204 LogiCore IP Guide that a minimal line rate of 1Gbps is mandatory. I am not familiar with FPGA design but it is critical for me to evaluate whether it is possible to configure the JESD204 Core to work with lower line rates.
Is that possible? What are the reasons behind the restricition of at least 1 Gbps line rates?
Kind Regards,
Bernhard
