05-18-2017 04:27 AM
Hello Xilinx Community,
this is my first post and I hope i got into the right forum. Thank you all in advance for your help.
At my company an ADC design is pending that must use a JESD204b Subclass 0 interface. To interface with the ADC a Xilinx XC7K70T is proposed. The line rates are somewhat low between 300 Mbps and 600 Mbps depending on the final configuration.
I have now read in the JESD204 LogiCore IP Guide that a minimal line rate of 1Gbps is mandatory. I am not familiar with FPGA design but it is critical for me to evaluate whether it is possible to configure the JESD204 Core to work with lower line rates.
Is that possible? What are the reasons behind the restricition of at least 1 Gbps line rates?
05-29-2017 09:33 AM
I would also be interested in the answer.
In my understanding the JESD204B core is pure logic, therefor it should run at any speed. But there might be a minimal line rate limit given by the MGT transceiver.
05-30-2017 03:43 AM
Yes transceivers do have a min line rate of 500Mbps.
05-31-2017 06:51 AM
thank you for your reply.
If the receivers do have a minimal line rate of 500Mbps, why is the JESD204b interface restricted to 1Gbps?
Is there a possibility to perform oversampling to accomplish lower line rates or use HP I/Os instead of the GTX ones?