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Observer eldrick
Observer
484 Views
Registered: ‎07-24-2018

JESD204B Multibank Clock Sharing

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I am interfacing with an ADC (AD54J66) and DAC (DAC38J84) via the JESD204B IP on a ZCU102.

 

I have succeeded in verifying both RX and TX independently with the RX and TX configured for 2 lanes (thus all lanes and the input reference clocks are within the same GTH Bank, for TX this is Bank 130 on HPC1 and for RX this is Bank 229. Both banks receive their reference clocks from FMC_HPCx_GBTCLK0). In both cases I have seen the core report CPLL Lock via the debug ports and the JESD204B IP leaves the reset state.

 

I am in the process of combining both RX and TX into the same project and am now using the JESD204B IP Core with 8 lanes each, thus each IP Core instance utilizes 2 banks. The CPLL lock never asserts high and the core never leaves reset - pointing to the fact that there is a problem with the incoming reference clocks. I suspect the issue may lie in sharing the single input reference clocks amongst the banks, since each GBTCLK0 only routes to Bank 130 and 229 respectively in my setup. Would the Xilinx tools automatically share this clock to Banks 129 and 228? The IP Core has only 1 refclk differential pair input and I assume this would be the case. What am I missing here?

 

Thanks,

Eldrick

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Observer eldrick
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450 Views
Registered: ‎07-24-2018

Re: JESD204B Multibank Clock Sharing

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Final Update:

 

You can actually use two JESD204B Shared Logic in Core instances in the same project! After double checking my design it turns out I had configured the drpclk for both IPs for the wrong value. Future readers - double check this clock and the refclk if your core won't leave the reset state. Even with the critical warnings about conflicting placement constraints, the final implemented design seems to be fine. Examining the device view shows the proper GT banks to be routed and clocked.

 

 

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Observer eldrick
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Registered: ‎07-24-2018

Re: JESD204B Multibank Clock Sharing

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From this thread, it seems that my problem is actually in instantiating two JESD204B instances with both having Shared Logic in Core. I receive this critical warning during Implementation that suggests a conflict in GT placement:

 

---

[Vivado 12-2285] Cannot set LOC property of instance 'd1_bd_i/jesd204_rx/inst/i_jesd204_phy/inst/jesd204_phy_block_i/d1_bd_jesd204_1_0_phy_gt_i/inst/gen_gtwizard_gthe4_top.d1_bd_jesd204_1_0_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST'... Instance d1_bd_i/jesd204_rx/inst/i_jesd204_phy/inst/jesd204_phy_block_i/d1_bd_jesd204_1_0_phy_gt_i/inst/gen_gtwizard_gthe4_top.d1_bd_jesd204_1_0_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y4 because the bel is occupied by d1_bd_i/jesd204b_tx/inst/i_jesd204_phy/inst/jesd204_phy_block_i/d1_bd_jesd204_0_0_phy_gt_i/inst/gen_gtwizard_gthe4_top.d1_bd_jesd204_0_0_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["/home/eldrick/XilinxProjects/d1/d1.srcs/sources_1/bd/d1_bd/ip/d1_bd_jesd204_1_0/ip_0/ip_0/synth/d1_bd_jesd204_1_0_phy_gt.xdc":68]

---

 

Thanks @jmcclusk.

 

In order to have an RX and TX JESD204B Core present, do both need to be created with shared logic in example design or is there a way to change the constraints such that the transceivers are properly mapped to separate banks? (RX on Banks 228/229, TX on Banks 129/130).

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Observer eldrick
Observer
451 Views
Registered: ‎07-24-2018

Re: JESD204B Multibank Clock Sharing

Jump to solution

Final Update:

 

You can actually use two JESD204B Shared Logic in Core instances in the same project! After double checking my design it turns out I had configured the drpclk for both IPs for the wrong value. Future readers - double check this clock and the refclk if your core won't leave the reset state. Even with the critical warnings about conflicting placement constraints, the final implemented design seems to be fine. Examining the device view shows the proper GT banks to be routed and clocked.

 

 

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