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Observer tobias_w
Observer
5,243 Views
Registered: ‎11-17-2016

JESD204B RX example design

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Hi all,

 

I want to implement a JESD204B reciever design in VIVADO 2016.3. Therefore I create a JESD204B IP-core with the settings:

L = 1, F = 2, K = 32 , SYSREF off and SCR off. I used right click on the block with "open IP example design". To understand which signals the IP core need for simulation I run the example design simulation for 100 µs. After all register writes are done at the beginning of the simulation and a 0x1 was written in the reset register (0x004) the IP-core doesn´t leave the reset state.  Here is a screenshot of the simulation:

 

example_sim.PNG

 

There is still a 0x00000001 in the 0x004 register. Can you tell me whats going wrong and how I can fix it?

 

Best Regards

Tobias_w

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Explorer
Explorer
9,571 Views
Registered: ‎02-22-2012

Re: JESD204B RX example design

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My first steps to get familiar with JESD204 Xilinx IP core 7.0 was also via pg066 and Example Design. I used Vivado 2016.1 to generate Example Design for RX JESD204B and the simulation runs OK for me. My first problem with Example Design was similar to yours. I just need to run simulation for longer time. 100us is to short to finish JESD synchronization and connection. Extending simulation time (e.g. to 10ms) make my JESD204 Example Design simulation run to end with "Test passed" message.

p.s.

We just developed HW, FPGA and SW with AD9680-500 JESD204B ADC with z7035 and it is working OK. Behavior on real HW (link connection, status signals, data, ...) is the same as simulation shows, so I strongly suggest you to get familiar with all JESD204 Example Design is doing (synchronization, simulation of link data, ...). It is good example design.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: JESD204B RX example design

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you can find some example design here
https://www.xilinx.com/member/jesd204_eval.html
Thanks and Regards
Balkrishan
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Observer tobias_w
Observer
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Registered: ‎11-17-2016

Re: JESD204B RX example design

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Hello Balkrishan,

 

thanks for your post. I knew this link and the example designs. In the product guide of the JESD204 IP-core (PG066) is written that the simple example design is a good start for implementation. I already want to start with this. So can you tell me why the reciever core didn´t came out of the reset state?

 

Best Regards

Tobias_w

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Highlighted
Explorer
Explorer
9,572 Views
Registered: ‎02-22-2012

Re: JESD204B RX example design

Jump to solution

My first steps to get familiar with JESD204 Xilinx IP core 7.0 was also via pg066 and Example Design. I used Vivado 2016.1 to generate Example Design for RX JESD204B and the simulation runs OK for me. My first problem with Example Design was similar to yours. I just need to run simulation for longer time. 100us is to short to finish JESD synchronization and connection. Extending simulation time (e.g. to 10ms) make my JESD204 Example Design simulation run to end with "Test passed" message.

p.s.

We just developed HW, FPGA and SW with AD9680-500 JESD204B ADC with z7035 and it is working OK. Behavior on real HW (link connection, status signals, data, ...) is the same as simulation shows, so I strongly suggest you to get familiar with all JESD204 Example Design is doing (synchronization, simulation of link data, ...). It is good example design.

0 Kudos