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Visitor geerard
Visitor
9,010 Views
Registered: ‎07-25-2016

KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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I'm trying to connect the KC705 board with a PC using the SFP+ connector and the Xilinx ten_gig_eth_pcs_pma IP core. I'm struggling with the clock.

 

(1) Is it possible to use the on-board clocks for this purpose? If so, how? I've tried the USER_CLOCK, which is pre-configured to be 156.250 MHz at power-up, but this is not working due to the placement of the ip-core, which is in another block as the USER_CLOCK. I've also tried using a PLL and a MMCM using the clocking wizard to create the correct clock frequency. At last, I've tried to connect the SYSCLK using an IBUFGDS (although this clock is a 200 MHz clock). None of these solutions are working in my setup. Has someone succeeded in doing this?

In my last attempt, I moved the IBUFDS_GTE2 from the ten_gig_eth_pcs_pma_0_shared_clock_and_reset entity out of this entity, to my top-level, such that I preform the conversion from differential to single-ended in the top-level sheet.

(2) Should there be an IBUF in front of the inputs of a IBUFDS_GTE2? Neither with or without IBUF buffer seems to work.

 

I'm using the KC705, running Vivado 2015.4 on CentOS 6.8. The 10G Ethernet PCS/PMA (10GBASE-R/KR) core has following parameters:

64-bit XGMII datapath

156.25MHz clocking (no additional transceiver control and status ports)

Shared logic included in example design

No MDIO Management features

 

Best regards,

Dave G.

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Adventurer
Adventurer
16,350 Views
Registered: ‎02-24-2012

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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Hi @geerard

 

I got it running on the VC707 which is similar to the KC705. You need to use the SI5324 PLL on the board configured in free running mode to get the 156.25MHz reference clock. However, you have to configure it via I2C. I used the following software from SiLabs, but I can share a working register configuration if needed:

 

http://www.silabs.com/Support%20Documents/Software/PrecisionClock_EVBSoftware.zip

 

Connect this differential reference clock to the IBUFDS_GTE2 (I/IB). Output port O goes to the QPLL instance and to a BUFG instance to drive clock for all the other logic. Don't forget to set attributes CLKRCV_TRST, CLKCM_CFG and CLKSWING_CFG of IBUFDS_GTE2 to default values or the QPLL might not lock cause of missing termination. See page 34 here:

 

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

Hope that helps.

 

Best Regards,

 

Stephan

8 Replies
Adventurer
Adventurer
16,351 Views
Registered: ‎02-24-2012

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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Hi @geerard

 

I got it running on the VC707 which is similar to the KC705. You need to use the SI5324 PLL on the board configured in free running mode to get the 156.25MHz reference clock. However, you have to configure it via I2C. I used the following software from SiLabs, but I can share a working register configuration if needed:

 

http://www.silabs.com/Support%20Documents/Software/PrecisionClock_EVBSoftware.zip

 

Connect this differential reference clock to the IBUFDS_GTE2 (I/IB). Output port O goes to the QPLL instance and to a BUFG instance to drive clock for all the other logic. Don't forget to set attributes CLKRCV_TRST, CLKCM_CFG and CLKSWING_CFG of IBUFDS_GTE2 to default values or the QPLL might not lock cause of missing termination. See page 34 here:

 

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

Hope that helps.

 

Best Regards,

 

Stephan

Visitor geerard
Visitor
8,962 Views
Registered: ‎07-25-2016

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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Hi @tud_hartmann,

 

Thank you for your extended clarification. The VC707 indeed has the exact same PLL circuit and crystal. If you could share the register configuration, that would be very nice! I think more people will have this issue and will have to set the values for the 48 registers of the Si5324/26.

 

Regards,

Dave G.

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Adventurer
Adventurer
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Registered: ‎02-24-2012

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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Hi  @geerard,

 

here is my Verilog array with the configuration for all PLL registers:

 

 

reg [15:0] pll_cfg[0:42];

initial
  begin
    //              addr,   data
     pll_cfg[ 0] = {8'd0,   8'h54};
     pll_cfg[ 1] = {8'd1,   8'hE4};
     pll_cfg[ 2] = {8'd2,   8'h12};
     pll_cfg[ 3] = {8'd3,   8'h15};
     pll_cfg[ 4] = {8'd4,   8'h92};
     pll_cfg[ 5] = {8'd5,   8'hED};
     pll_cfg[ 6] = {8'd6,   8'h2F};
     pll_cfg[ 7] = {8'd7,   8'h2A};
     pll_cfg[ 8] = {8'd8,   8'h00};
     pll_cfg[ 9] = {8'd9,   8'hC0};
     pll_cfg[10] = {8'd10,  8'h08};
     pll_cfg[11] = {8'd11,  8'h40};
     pll_cfg[12] = {8'd19,  8'h29};
     pll_cfg[13] = {8'd20,  8'h3E};
     pll_cfg[14] = {8'd21,  8'hFE};
     pll_cfg[15] = {8'd22,  8'hDF};
     pll_cfg[16] = {8'd23,  8'h1F};
     pll_cfg[17] = {8'd24,  8'h3F};
     pll_cfg[18] = {8'd25,  8'hA0};
     pll_cfg[19] = {8'd31,  8'h00};
     pll_cfg[20] = {8'd32,  8'h00};
     pll_cfg[21] = {8'd33,  8'h03};
     pll_cfg[22] = {8'd34,  8'h00};
     pll_cfg[23] = {8'd35,  8'h00};
     pll_cfg[24] = {8'd36,  8'h03};
     pll_cfg[25] = {8'd40,  8'hC2};
     pll_cfg[26] = {8'd41,  8'h49};
     pll_cfg[27] = {8'd42,  8'hEF};
     pll_cfg[28] = {8'd43,  8'h00};
     pll_cfg[29] = {8'd44,  8'h77};
     pll_cfg[30] = {8'd45,  8'h0B};
     pll_cfg[31] = {8'd46,  8'h00};
     pll_cfg[32] = {8'd47,  8'h77};
     pll_cfg[33] = {8'd48,  8'h0B};
     pll_cfg[34] = {8'd55,  8'h00};
     pll_cfg[35] = {8'd131, 8'h1F};
     pll_cfg[36] = {8'd132, 8'h02};
     pll_cfg[37] = {8'd137, 8'h01};
     pll_cfg[38] = {8'd138, 8'h0F};
     pll_cfg[39] = {8'd139, 8'hFF};
     pll_cfg[40] = {8'd142, 8'h00};
     pll_cfg[41] = {8'd143, 8'h00};
     pll_cfg[42] = {8'd136, 8'h40};
  end // initial begin

 

Best Regards,

 

Stephan

 

Visitor geerard
Visitor
8,843 Views
Registered: ‎07-25-2016

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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Hi Stephan,

 

Still no luck with the free running clock from the Si5324. I tried following steps:

- I supplied a 156.25MHz clock to the REC_CLOCK (CKIN1) input of the Si5324, although your settings use the external crystal

- I've put the Si5326_RST to a high value.

- I've set the IO Standard of the SI5326_OUT_C_P/N signals to be LVDS_25

- I configured the I2C MUX to enable channel 7 (to the Si5324), got an ACK

- I configured the 43 parameters using your settings, got 43 ACK's.

- I changed the attributes of the IBUFDS_GTE2, as in your first post.

 

When I set the Si5324 in bypass mode (REG 1), it returns me a clock ! Currently, I have no idea about the stability, but for now I can continue !

 

Thank you for the help !

 

Regards,

Dave

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Adventurer
Adventurer
8,523 Views
Registered: ‎02-24-2012

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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@geerard

Hi Dave,

 

I just found some time to test our 10G Ethernet design on a KC705 board and it can establish a link with a 10G Ethernet switch. This means, that the Si5324 configuration is correct for free running mode. I somewhere read, that the Si5324 needs a proper reset. Can you try to generate a reset pulse instead of tying it to 1?

 

Best Regards,

 

Stephan

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Visitor geerard
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Registered: ‎07-25-2016

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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@tud_hartmann,

Hi Stephan,

 

I've tried resetting the Si5324 properly, and reassigned the parameters to the ones you provided and indeed, now it's generating the proper clock ! I've also made sure that the clock towards the Si5324 was disabled again (REC_CLOCK on FPGA / CKIN1 on Si5324).

 

Thank you !

 

Can I ask what block you have connected to the XGMII port? Is it a custom one, or an IP core? I try to generate Ethernet frames from the FPGA to a PC using a direct link, but without luck. I checked the receiver with wireshark, but I am not receiving my own Ethernet packets. The other direction (PC to FPGA) is working for some keep-alive packets (UDP broadcast packets every 15 sec).

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Adventurer
Adventurer
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Registered: ‎02-24-2012

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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@geerard

 

Sorry for late response. We have connected our own 10G Ethernet MAC to the XGMII ports and it works with a 10G Ethernet NIC (Chelsio). However, it took some weeks to get it working cause it is hard to debug.

 

Best Regards,

 

Stephan

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Visitor geerard
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Registered: ‎07-25-2016

Re: KC705 sfp+ 10 gigabit ethernet pcs/pma clock

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@tud_hartmann

 

Thanks for the response. I created a XGMII driver (MAC-layer) myself, creating Ethernet packages. Initially, the checksum was wrong, and our NIC (Synology E10G15-F1) does checksum offloading, so packets containing an invalid checksum never arrive to Wireshark. Additionally, the XGMII interface translates a start control byte into the first ethernet preamble byte, which I wasn't aware of.

 

Currently, my interface is working, but I should still perform some measurements to detect the maximum throughput.

 

Thanks for the help, it was really appreciated !

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